ACE9050 Datasheet, PDF (15/52 Pages) Mitel Networks Corporation – System Controller and Data Modem Advance Information

The ACE9050 has an additional Output Port 2, which is
separate from the 6303 Port 2.
Associated Registers
Name
Description
DDR2*
Bits [4:0]
1: Sets corresponding Port line to output
0: Sets corresponding Port line to input
Port 2*
Bits [4:3]
Read and Write access to Port 2
*The TRCSR register overrules these registers.
Table 14 Port 2 associated registers
Programmable Timer
The ACE9050 6303R contains a 16 bit programmable timer
which may measure the period of an input waveform, as with a
standard 6303R. This counter runs from the ECLK. The counter
cannot generate an output waveform. The input to the timer is
internally connected to the IFC counter for the AFC loop function.
The timer hardware consists of an 8-bit status and control
register, a 16-bit free running counter and a 16-bit input capture
register.
TCSR (Timer Control and Status Register)
The Control and Status register has three flags: Input capture,
Output Compare Match and Timer Overflow. Each flag has an
associated interrupt enable. The other two bits in the register are
for control of the output level and input edge select. The bits are
described in Table 15.
Bit R/W Name
Description
7 R ICF Transition of appropriate type occurred
on input (ICN). Cleared by read of Input
Capture register
6 R OCF Match between Free Running Counter
and Output Compare Register*
5 R TOF Timer overflow. Cleared by read of
counter.
4 R/W EICI Enable an ICF interrupt
3 R/W EOCI Enable an OCF interrupt*
2 R/W ETOI Enable Timer overflow interrupt
1 R/W IEDG 0 = Negative edge on ICN trigger ICR
1 = Positive edge on ICN trigger ICR
0 R/W OLVL _{Output level*}
*As the timer cannot generate an output these bits are considered non-
functional in the ACE9050.
Table 15 TCSR bit descriptions
FRC: Free Running Counter
The FRC is a 16-bit ReadWrite counter; Data can be read
from or written to it. The register has extra hardware to load and
save both bytes of the counter simultaneously when a double
byte store instruction is used. The counter is incremented by the
processor clock. Reading from the counter does not affect it.
ICR: Input Capture Register
The ICR is a16-bit Read register which holds the value of the
Free Running Counter when a transition is detected on ICN, i.e.
the IFC Counter Output.
ACE9050
Serial Communication Interface (SCI or UART)
The processor contains a full-duplex asynchronous Serial
Communications interface. It consists of a transmitter and receiver
which operate independently but with the same data format and
rate. Both parts communicate with the CPU via the data bus and
to the outside world via Port 2. Interrupts generated can be
individually masked. The receiver can be sent to ‘sleep’ by
software. No receive interrupts are generated during a message
in this state. The Baud rate can be generated within the
ACE9050 6303 or the ACE9050 can provide a baud rate
generator and selection register external to the processor block.
This allows the following standard baud rates to be programmed:
600,1200. 2400, 4800 or 9600.
The hardware consists of four registers: an 8-bit control/
status register, 4-bit mode select, an 8-bit receive data and an 8-
bit transmit data register.
Bit R/W Name
Description
7 R RDRF RX Data Register Full*
6 R ORFE Overrun/Framing Error*
5 R TDRE TX Data Register Empty
4 R/W RIE RX Interrupt Enable: Enables an interrupt
for both Bit 7 and Bit 6
3 R/W RE RX Enable. This sets Port2 bit 3 to Input
regardless of the DDR2
2 R/W TIE TX Interrupt enable: Bit 5 will generate
an Interrupt
1 R/W TE TX Enable: This sets Port2 bit 4 to Output
regardless of DDR2
0 R/W WU Wake Up: Set by software and cleared
by hardware.**
* Overrun is where new data is placed in the Receive register before
the old data has been read. Framing Error is where the bit counter
is not synchronised with the boundary of the byte in the Received
bit stream defined in Table 17.
** The Wake Up mode is intended for systems where more than one
Processor is on the UART link, and is addressed by the first byte of
data. If the address is incorrect the processor can disable the
interrupts and effectively ignore the word.
Table 16 TRCSR: Transmit/Receive Control Status Register
bit descriptions
Condition
Bit 7 Bit 6
No Data
Good Data RX
Framing error
Overrun error
00
10
01
11
NOTE:
Bits 7 and 6 are cleared by reading the
Status register, followed by reading the
Received Data register
Table 17
RMCR Transfer Rate/Mode Control Register
The mode select register controls the clock source and set-
up. This is a write-only register. The processor can use an
internally divided down processor clock to give the Baud clock.
The Baud rate division ratio can be set to a value from 16 to 4096.
However, this could lead to non-standard Baud rates so the
ACE9050 provides a separate Baud rate generator.The bit
functions of this register are described in Table 18.
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