ACE9050 Datasheet, PDF (30/52 Pages) Mitel Networks Corporation – System Controller and Data Modem Advance Information

ACE9050
4. Transmit Stop When all bytes have been transmitted the STP
bit should be set. The ACE9050 I²C will then transmit a STOP
condition, clear the STP bit and return to the idle state. If the Slave
receiver cannot receive any more data it must indicate this to the
Master by generating the Not Acknowledged condition.
Master Receive
In the Master receive mode the ACE9050 I²C will receive a
number of bytes from a Slave transmitter. The sequence is not
dissimilar to that for Transmit. For some memory devices a
‘dummy write’ may be required to transmit the word address
before the read operation.
Before the master receiver mode can be entered the
I2C_CNTR register should be initialised as for enterinq master
transmit mode.
1. Transmit Start Condition The master receive mode is
entered by setting the STA bit to one. The ACE9050 I²C will then
test the I²C bus and will transmit a START condition when the bus
is free. After the START condition has been transmitted the IFLG
bit will be set and status code 08_H will be in the I2C_STAT
register. If a repeated START condition has been transmitted
then the status code will be 10_H instead of 08_H .
2. Transmit Slave address and Read The I2C_DATA register
should be loaded with the address of the Slave in bits[7:1] and
bit[0] set to 1 to specify read. The IFLG bit should now be cleared
to 0 before the transfer can continue. When the Slave address
and read bit have been transmitted and an acknowledge bit
received, the IFLG bit will be set again. A number of status codes
are possible in the STAT register; these are shown in Tables 51
and 52.
3. Receive Data If the code 40_H has been detected it can be
assumed that a Slave has detected its address and when the
IFLG is cleared the ACE9050 will begin to clock in valid data
on the SDA line. After each data byte has been received the
IFLG will be set, and require clearing. One of three status
codes wil be in the I2C_STAT register, as shown in Tables 53
and 54.
Code
ACE9050 I²C state
Micro response
Next I²C action
40_H Addr and Read transmitted, ACK received Clear IFLG, AAK = 0
Clear IFLG, AAK = 1
Receive Data byte, transmit Not ACK
Receive Data byte, transmit ACK
48_H Addr and Write transmitted, ACK not received (a) Set STA, clear IFLG
(b) Set STP, clear IFLG
Transmit repeated START
Transmit STOP
(b) Set STA and STP, clear IFLG Transmit STOP then START
Table 51 Possible status codes after Slave address has been transmitted with the ACE9050 as the only bus Master
Code
ACE9050 I²C state
Micro response
Next I²C action
38_H As for Master transmit
68_H
78_H
B0_H
As for Master transmit
As for Master transmit
Table 52 Possible extra status codes after Slave address has been transmitted with multiple bus Masters
Code
ACE9050 I²C state
Micro response
Next I²C action
50_H Data byte received, ACK transmitted Read Data, clear IFLG, AAK = 0
Read Data, clear IFLG, AAK = 1
ReceiveData byte, transmit Not ACK
Receive Data byte, transmit ACK
58_H Data byte received, Not ACK transmitted (a) Read Data, set STA, clear IFLG Transmit repeated START
(b) Read Data, set STP, clear IFLG Transmit STOP
(b) Read Data, set STA and STP,
Transmit STOP then START
clear IFLG
Table 53 Possible status codes after Data has been received in multi-Master system
Code
ACE9050 I²C state
Micro response
Next I²C action
38_H Arbitration lost
As for Master transmit
As for Master transmit
Table 54 Possible status codes after Data has been received in multi-Master system
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