VP305 Datasheet, PDF (69/85 Pages) Mitel Networks Corporation – Satellite Channel Decoder

1st byte packet n
MCLK
MDO7:0
MOSTRT
MOVAL
DRAFT - PRELIMINARY DATA
VP305/6
188th byte packet n
1st byte packet n+1
BKERR
Tp
Ti
Fig. 24. VP305/6 output data wave form diagram.
MCLK will be a continuously running clock once symbol lock has been achieved in the QPSK
block and is derived from the symbol clock.
MCLK is the output interface byte rate clock, running at a rate given by the table on page 70. The
maximum jitter in the packet synchronisation byte is limited to one output clock period.
All output data and signals (MDO7:0, MOSTRT, MOVAL, BKERR ) change on the negative edge
of MCLK to present stable data and signals on the positive edge of the clock.
A complete packet of data is output on MDO7:0 on 188 consecutive clocks and the MDO7:0 pins
will remain low during the inter packet gaps.
MOSTRT goes high for the first byte clock of a packet.
MOVAL will go high on the first byte of a packet and remain high until the 188^th byte has been
clocked out.
BKERR will go low on the first byte of a packet where uncorrectable bytes are detected and
remain low until the 188^th byte has been clocked out.
Tp is equivalent to 188 clock cycles irrespective of the code rate.
Ti depends on the inner code rate (1/2, 2/3, 3/4, 5/6 or 7/8).
The following table shows data output timing and an example of the data rate on MDO7:0 for a
maximum input symbol rate (Rs) of 30Msym/sec.
The duplication or disclosure of data contained on this sheet is subject to the restrictions
on the title page of this document.
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