VP305 Datasheet, PDF (58/85 Pages) Mitel Networks Corporation – Satellite Channel Decoder

VP305/6
DRAFT - PRELIMINARY DATA
3. MICROPROCESSOR CONTROL.
Selection of the microprocessor interface type is controlled by the SER pin.
SER
0
1
interface type
I²C bus interface
Parallel interface
3.1. I²C bus Interface.
Not available on VP305.
The I²C bus serial interface (ref. 2.) uses pins:
SDA Serial data, the most significant bit is sent first.
SCL Serial clock (D0).
The I²C bus Address is 0001 110 R/ W .
The circuit works as a slave transmitter with the eighth bit set high or as a slave receiver with the
eighth bit set low. In receive mode, the first data byte is written to RADD register, which forms the
register sub-address.
Bit 7 of the RADD register, IAI is an Increment Auto Inhibit function. When the IAI bit is set high,
the automatic incrementing of register addresses is inhibited. IAI set low is the normal situation so
that data bytes sent on the I²C bus after the RADD register data are loaded into successive
registers. This automatic incrementing feature avoids the need to individually address each
register.
Following a valid chip address, the I²C bus STOP command resets the RADD register to 01. If the
chip address is not recognised, the VP306 will ignore all activity until a valid chip address is
received. The I²C bus START command does NOT reset the RADD register to 01. This allows a
combined I²C bus message, to point to a particular read register with a write command, followed
immediately with a read data command. If required, this could next be followed with a write
command to continue from the latest address. RADD would not be sent in this case. Finally a
STOP command should be sent to free the bus.
When the I²C bus is addressed (after a recognised STOP command) with the read bit set, the first
byte read out shall be the content of register 01. To access the chip identification in register 00,
the microprocessor should send the chip address with the write bit set, followed by the register
address 00, then a restart with the read bit set, followed by a data read.
The duplication or disclosure of data contained on this sheet is subject to the restrictions
on the title page of this document.
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