VP305 Datasheet, PDF (27/85 Pages) Mitel Networks Corporation – Satellite Channel Decoder

DRAFT - PRELIMINARY DATA
VP305/6
2.5. BANK 0: Monitor QPSK read registers.
2.5.1. ID: Identification register.
Parallel mode -
Bank 0-7. Address 0.Type Read.
Serial mode - Addresses 00, 08, 16, 24, 32, 40, 48, 56.
7
6
5
4
3
2
1
0
R/W
ID[7:0] Chip identification
R
ID[7:0]
Identification: 0 = VP305/6 version.
2.5.2. INT_QPSK: Interrupt for QPSK block, register.
These bits indicate the QPSK block event causing the interrupt signalled by the IRQ line going
low. The IRQ line is reset high and the register is reset to zero when the INT_QPSK register is
read. The events can be masked from activating both the INT_QPSK register bit and the IRQ
line by setting the appropriate event masking bit LOW in the IE_QPSK (interrupt enable) register,
see page 31. All bits in the IE_QPSK register should be set high.
Parallel mode -
Bank 0. Address 1. Type Read.
Serial mode - Address 01.
7
6
5
4
3
2
1
0
INT_QPSK[7:0]
INT_QPSK[0] High = Symbol AFC lock is detected. This means that the number of clock VCO
cycles measured during the reference period set by SYM_RP register is in the range
SYM_NF (register) ±2 range.
INT_QPSK[1] High = Symbol AFC lock is lost.
INT_QPSK[2] High = Carrier Phase lock is detected.
INT_QPSK[3] High = Carrier Phase lock is lost.
INT_QPSK[4] High = Carrier Frequency lock is detected.
INT_QPSK[5] High = Carrier Frequency lock is lost.
INT_QPSK[6] High = Frequency sweep has reached its lower limit.
INT_QPSK[7] High = Frequency sweep has reached its upper limit.
The duplication or disclosure of data contained on this sheet is subject to the restrictions
on the title page of this document.
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