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PDSP16318_96 Datasheet, PDF (6/8 Pages) Mitel Networks Corporation – Complex Accumulator
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PDSP16318/16318A
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb (Commercial) = 0°C to +70°C, VCC = 5.0V ± 5%, GND = 0V
Tamb (Industrial) =-40°C to +85°C, VCC = 5.0V ± 10%, GND = 0V
Tamb (Military) =-55°C to +125°C, VCC = 5.0V ± 10%, GND = 0V
STATIC CHARACTERISTICS
Characteristic
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input leakage current
Output leakage current
Output SC current
Input capacitance
Symbol
VOH
VOL
VIH
VIL
IIL
loz
IOS
CIN
Min.
2.4
-
3.5
-
-10
-50
20
-
Value
Typ.
-
-
9
Max.
-
0.4
-
0.5
+10
+50
200
-
Units
V
V
V
V
µA
µA
mA
pF
Conditions
IOH = 3.2mA
lOL=-3.2mA
GND < VIN<VCC
GND <VOUT < VCC
Vcc = Max
SWITCHING CHARACTERISTICS
Characteristic
Value
Industrial + Commercial
Value
Military
PDSP16318 PDSP16318A PDSP16318
Min. Max. Min. Max. Min. Max.
Units
Conditions
Clock period
Clock High Time
Clock Low Time
A15:0, B15:0 setup to clock rising edge
A15:0, B15:0 hold after clock rising edge
MS, S2:0, ASI setup to clock rising edge
DEL, ASR, CLR setup to clock rising edge
DEL, ASR, CLR, MS, S2:0, ASI hold after
clock rising edge
100 - 50 - 100 -
20 -
15 - 20
-
20 -
15 - 20
-
8
-
5
-
8
-
2
-
2
-
2
-
10 -
10 - 10
-
8
-
5
-
8
-
2
-
2
-
2
-
CEA, CEB setup to clock falling edge
2
-
2
-
2
-
CEA, CEB hold after clock rising edge
8
-
8
-
8
-
Clock rising edge to OVR, C15:0, D15:0
5 40
5 30 5
40
OEC/OED low to C15:0/D15:0 high data valid
- 40
- 30 -
40
OEC/OED low to C15:0/D15:0 low data valid
- 40
- 30 -
40
OEC/OED high to C15:0/D15:0 high impedance - 40
- 30 -
40
Vcc current
- 70
- 110 -
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns 2 x LSTTL + 20pF
ns 2 x LSTTL + 20pF
ns 2 x LSTTL + 20pF
ns 2 x LSTTL + 20pF
mA VCC = max,
TTL input levels
Outputs unloaded,
fCLK = max
Vcc current
- 30
- 60 -
30
mA VCC = max,
CMOS input levels
Outputs unloaded,
fCLK = max
NOTES
1. LSTTL is equivalent to IOH = 20 microamps, IOL = -0.4mA
2. Current is defined as negative into the device
3. CMOS input levels are defined as:
VIL = 0.5
VIH = VDD - 0.5
6
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