PDSP16318_96 Datasheet, PDF (3/8 Pages) Mitel Networks Corporation – Complex Accumulator

Symbol
A15:0
B15:0
C15:0
D15:0
CLK
CEA
CEB
OEC
OED
OVR
ASR1:0
ASI1:0
CLR
MS
S2:0
DEL
VCC
GND
Type
Input
Input
Output
Output
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Input
Input
Power
Ground
PDSP16318/13618A
Description
Data presented to this input is loaded into the input register on the rising edge of CLK. A15 is the MSB.
Data presented to this input is loaded into the input register on the rising edge of CLK. B15 is the MSB
and has the same weighting as A15.
New data appears on this output after the rising edge of CLK. C15 is the MSB.
New data appears on this output after the rising edge of CLK. C15 is the MSB.
Common Clock to all internal registers
Clock enable: when low the clock to the A input register is enabled.
Clock enable: when low the clock to the B input register is enabled.
Output enable: Asynchronous 3-state output control: The C outputs are in a high impedance
state when this input is high.
Output enable: Asynchronous 3-state output control: The D outputs are in a high impedance
state when this input is high.
Overflow flag: This flag will go high in any cycle during which either the output data overflows the number
range selected or either of the adder results overflow. A new OVR appears after the rising edge of the
CLK.
Add/subtract Real: Control input for the 'Real' adder. This input is latched by the rising edge of clock.
Add/subtract Imag: Control input for the 'Imag' adder. This input is latched by the rising edge of clock.
Accumulator Clear: Common accumulator clear for both Adder/Subtractor units. This input is latched by
the rising edge of CLK.
Mux select: Control input for both adder multiplexers. This input is latched by the rising edge of CLK.
When high the feedback path is selected.
Scaling control: This input selects the 16-bit field from the 20-bit adder result that is routed to the outputs.
This input is latched by the rising edge of CLK.
Delay Control: This input selects the delayed input to the real adder for operations involving the
PDSP16112. This input is latched by the rising edge of CLK.
+5V supply: Both Vcc pins must be connected.
0V supply: Both GND pins must be connected.
GG pin AC pin Function GG pin AC pin Function GG pin AC pin Function GG pin AC pin Function
77
B2
D7
6
K2
C7
31
K10
A1
82
C2
D8
7
K3
C6
32
J10
A2
83
B1
D9
8
L2
C5
33
K11
A3
84
C1
D10
9
L3
C4
34
J11
A4
85
D2
GND
10
K4
C3
35
H10
A5
86
D1
VCC
11
L4
C2
36
H11
A6
87
E3
D11
12
J5
C1
37
F10
A7
88
E2
D12
13
K5
C0
38
G10
A8
89
E1
D13
14
L5
OED
39
G11
A9
90
F2
D14
15
K6
OEC
40
G9
A10
91
F3
D15
16
J6
S2
41
F9
A11
92
G3
C15
17
J7
S1
42
F11
A12
93
G1
C14
18
L7
S0
43
E11
A13
94
G2
C13
19
K7
MS
44
E10
A14
95
F1
C12
20
L6
ASI1
45
E9
A15
96
H1
VCC
21
L8
ASI0
46
D11
CEA
97
H2
GND
22
K8
DEL
47
D10
B15
98
J1
C11
23
L9
CLR
48
C11
B14
99
K1
C10
24
L10
ASR1
49
B11
B13
100
J2
C9
25
K9
ASR0
50
C10
B12
5
L1
C8
26
L11
A0
51
A11
B11
56
B10
B10
57
B9
B9
58
A10
B8
59
A9
B7
60
B8
B6
61
A8
B5
62
B6
B4
63
B7
B3
64
A7
B2
65
C7
B1
66
C6
B0
67
A6
CLK
68
A5
CEB
69
B5
OVR
70
C5
D0
71
A4
D1
72
B4
D2
73
A3
D3
74
A2
D4
75
B3
D5
76
A1
D6
Device Pinout for ceramic 84 - pin PGA (AC84) and ceramic QFP (GG100)
3