MT9044 Datasheet, PDF (14/30 Pages) Mitel Networks Corporation – T1/E1/OC3 System Synchronizer

MT9044
Advance Information
locked to an external reference signal, but is
operating using storage techniques. For the
MT9044, the storage value is determined while the
device is in Normal Mode and locked to an external
reference signal.
The absolute Master Clock (OSCi) accuracy of the
MT9044 does not affect Holdover accuracy, but the
change in OSCi accuracy while in Holdover Mode
does.
Capture Range
Also referred to as pull-in range. This is the input
frequency range over which the synchronizer must
be able to pull into synchronization. The MT9044
capture range is equal to ±230ppm minus the
accuracy of the master clock (OSCi). For example, a
±32ppm master clock results in a capture range of
±198ppm.
Lock Range
This is the input frequency range over which the
synchronizer must be able to maintain
synchronization. The lock range is equal to the
capture range for the MT9044.
Phase Slope
Phase slope is measured in seconds per second and
is the rate at which a given signal changes phase
with respect to an ideal signal. The given signal is
typically the output signal. The ideal signal is of
constant frequency and is nominally equal to the
value of the final output signal or final input signal.
Time Interval Error (TIE)
TIE is the time delay between a given timing signal
and an ideal timing signal.
Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a
given timing signal and an ideal timing signal within a
particular observation period.
MTIE(S)= TIEmax(t) – TIEmin(t)
end of a particular observation period. Usually, the
given timing signal and the ideal timing signal are of
the same frequency. Phase continuity applies to the
output of the synchronizer after a signal disturbance
due to a reference switch or a mode change. The
observation period is usually the time from the
disturbance, to just after the synchronizer has settled
to a steady state.
In the case of the MT9044, the output signal phase
continuity is maintained to within ±5ns at the
instance (over one frame) of all reference switches
and all mode changes. The total phase shift,
depending on the switch or type of mode change,
may accumulate up to ±200ns over many frames.
The rate of change of the ±200ns phase shift is
limited to a maximum phase slope of approximately
5ns/125us. This meets the maximum phase slope
requirement of Bellcore GR-1244-CORE (81ns/
1.326ms).
Phase Lock Time
This is the time it takes the synchronizer to phase
lock to the input signal. Phase lock occurs when the
input signal and output signal are not changing in
phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is
affected by many factors which include:
i) initial input to output phase difference
ii) initial input to output frequency difference
iii) synchronizer loop filter
iv) synchronizer limiter
Although a short lock time is desirable, it is not
always possible to achieve due to other synchronizer
requirements. For instance, better jitter transfer
performance is achieved with a lower frequency loop
filter which increases lock time. And better (smaller)
phase slope performance (limiter) results in longer
lock times. The MT9044 loop filter and limiter were
optimized to meet the AT&T TR62411 jitter transfer
and phase slope requirements. Consequently,
phase lock time, which is not a standards
requirement, may be longer than in other
applications. See AC Electrical Characteristics -
Performance for maximum phase lock time.
Phase Continuity
Phase continuity is the phase difference between a
given timing signal and an ideal timing signal at the
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