MT9044 Datasheet, PDF (1/30 Pages) Mitel Networks Corporation – T1/E1/OC3 System Synchronizer

Features
• Supports AT&T TR62411 and Bellcore
GR-1244-CORE Stratum 3, Stratum 4
Enhanced and Stratum 4 timing for DS1
interfaces
• Supports ITU-T G.812 Type IV clocks for 1,544
kbit/s interfaces and 2,048 kbit/s interfaces
• Supports ETSI ETS 300 011, TBR 4, TBR 12
and TBR 13 timing for E1 interfaces
• Selectable 1.544MHz, 2.048MHz or 8kHz input
reference signals
• Provides C1.5, C2, C3, C4, C6, C8, C16, and
C19 (STS-3/OC3 clock divided by 8) output
clock signals
• Provides 5 different styles of 8 KHz framing
pulses
• Holdover frequency accuracy of 0.05 PPM
• Holdover indication
• Attenuates wander from 1.9Hz
• Provides Time Interval Error (TIE) correction
• Accepts reference inputs from two independent
sources
• JTAG Boundary Scan
Applications
• Synchronization and timing control for
multitrunk T1,E1 and STS-3/OC3 systems
• ST-BUS clock and frame pulse sources
OSCi
OSCo
TCLR
MT9044
T1/E1/OC3 System Synchronizer
Advance Information
DS5058
ISSUE 3
September 1999
Ordering Information
MT9044AP
MT9044AL
44 Pin PLCC
44 Pin MQFP
-40 to +85 °C
Description
The MT9044 T1/E1/OC3 System Synchronizer
contains a digital phase-locked loop (DPLL), which
provides timing and synchronization signals for
multitrunk T1 and E1 primary rate transmission links
and STS-3/0C3 links.
The MT9044 generates ST-BUS clock and framing
signals that are phase locked to either a 2.048MHz,
1.544MHz, or 8kHz input reference.
The MT9044 is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE Stratum 3, Stratum 4
Enhanced, and Stratum 4; and ETSI ETS 300 011. It
will meet the jitter/wander tolerance, jitter/wander
transfer, intrinsic jitter/wander, frequency accuracy,
capture range, phase change slope, holdover
frequency and MTIE requirements for these
specifications.
VDD VSS
TCK
TDI
TMS
TRST
TDO
PRI
SEC
RSEL
LOS1
LOS2
Master Clock
IEEE
1149.1a
TIE
Corrector
Circuit
Virtual
Reference
DPLL
Reference
Select
MUX
Reference
Select
Selected
Reference
TIE
Corrector
Enable
State
Select
State
Select
Input
Impairment
Monitor
Automatic/Manual
Control State Machine
Guard Time
Circuit
Output
Interface
Circuit
Feedback
Frequency
Select
MUX
APLL
MS1 MS2 RST HOLDOVER
GTo
GTi
FS1
FS2
Figure 1 - Functional Block Diagram
C19o
C1.5o
C3o
C2o
C4o
C6o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
ACKi
ACKo
1