PDSP16116 Datasheet, PDF (13/17 Pages) Mitel Networks Corporation – 16 X 16 Bit Complex Multiplier

PDSP16116
ELECTRICAL CHARACTERISTICS
The Electrical Characteristics are guaranteed over the following range of operating conditions, unless otherwise stated:
V_DD = 15V±10%, GND = 0V, T_AMB (Industrial) = 240°C to 185°C, T_AMB (Military) = 255°C to 1125°C
Static Characteristics
Characteristic
Symbol
Value
Units
Min. Typ. Max.
Conditions
Output high voltage
Output low voltage
Input high voltage
Input high voltage
Input low voltage
Input leakage current
Input capacitance
Output leakage current
Output short circuit current
V_OH
2·4
-
V I_OH = 8mA
V_OL
-
0·4
V I_OL = 28mA
V_IH
3·0
-
V CLK input only
V_IH
2·2
-
V All other inputs
V_IL
-
0·8
V
GND < V_IN < V_DD
I_IN
210
110 µA
C_IN
10
pF GND < V_OUT < V_DD
I_OZ
250
150 µA V_DD = 15·5V
I_OS
10
300 mA
Switching Characteristics
Characteristic
PDSP16116 PDSP16116A PDSP16116D
Symbol
Units Conditions Fig.
Min. Max. Min. Max. Min. Max.
P ports setup time
WTOUT1:0 setup time
GWR4:0 setup time
SFTA1:0 setup time
SFTR2:0 setup time
CEX or CEY setup time
CEX or CEY hold time
X or Y ports setup time
X or Y ports hold time
WTA, WTB, SOBFP or EOPSS setup time
WTA, WTB, SOBFP or EOPSS hold time
CONX or CONY setup time
CONX or CONY hold time
AR15:13 or AI15:13 setup time
AR15:13 or AI15:13 hold time
OSEL to valid P ports
OER or OEI high to PR or PI high to high Z
OER or OEI low to PR or PI low to high Z
OER or OEI low to PR or PI high Z to high
OER or OEI high to PR or PI high Z to low
CLK frequency
CLK period
CLK high time
CLK low time
V_DD current (CMOS input levels)
V_DD current (TTL input levels)
t_CP
t_CW
t_CG
t_CSFTA
t_CSFTR
t_CES
t_CEH
t_DS
t_DH
t_WS
t_WH
t_CONS
t_CONH
t_AS
t_AH
t_OP
t_OPHZ
t_OPLZ
t_OPZH
t_OPZL
f_CLK
t_CLK
t_CLKH
t_CLKL
I_DDC
I_DDT
5 45 5
5 30 5
5 30 5
5 60 5
5 50 5
11 -
8
-
0
-
11 -
8
-
2
-
14 -
8
-
0
-
14 -
8
-
0
-
14 -
8
-
0
-
- 35 -
- 35 -
- 45 -
- 22 -
- 24 -
10
100 - 50
30 - 12
20 - 12
- 60 -
- 100 -
23 5 23 ns 30pF
9
20 5 20 ns 30pF
20 5 20 ns 30pF
30 5 30 ns 30pF
9
28 5 28 ns 30pF
-
8
- ns
9
0
-
0 ns
9
-
8
- ns
9
0
-
2 ns
9
-
8
- ns
9
0
-
0 ns
9
-
8
- ns
9
0
-
0 ns
9
-
8
- ns
0
-
2 ns
20
-
20 ns 30pF
25
-
25 ns
10, 11
25
-
25 ns
10, 11
18
-
18 ns
10, 11
18
-
18 ns
10, 11
20
31·5 MHz
- 31·7 - ns
9
- 12
- ns
9
- 12
- ns
9
80
-
80 mA See Note 1
130 - 130
See Note 1
NOTES
1. V_DD = 15·5V, outputs unloaded, clock frequency = Max.
2. The PDSP16116B is specified as the PDSP16116A except that the maximum clock frequency is guaranteed at 25MHz, with a minimum
clock period of 40ns.
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