PDSP16116 Datasheet, PDF (12/17 Pages) Mitel Networks Corporation – 16 X 16 Bit Complex Multiplier

PDSP16116
CLK
OUTPUT P PORTS
OUTPUT SFTA1:0
INPUT DATA X AND Y
INPUT CONTROLS CEX AND CEY
INPUT CONTROLS CONX AND CONY
INPUT CONTROL WTB1:0
t_CP
VALID DATA
t_CSFTA
t_CLK
t_CLKH
t_CLKL
VALID DATA
t_CSFTA
t_DS
t_CES
t_CONS
t_WS
t_DH
t_CEH
t_CONH
t_WH
Fig. 9 Normal mode timing
OER AND OEI
OUTPUT P PORTS
t_OPLZ
HIGH Z
t_OPZL
HIGH Z
Fig. 10 Output tristate timing
t_OPZH
t_OPHZ
HIGH Z
Test
Delay from
output high
to output
high Z (t_OPHZ)
Delay from
output low
to output
high Z (t_OPLZ)
Delay from
output high Z
to output low
(t_OPZL)
Delay from
output high Z
to output high
(t_OPZH)
Waveform measurement level
VH
0·5V
VT = 0V
VT = VDD
0·5V
VL
1·5V
0·5V
0·5V
1·5V
V_H is the voltage reached when the output is driven high
VL is the voltage reached when the output is driven low
1·5k
VT
DUT
30p
Three state delay measurement load
Fig. 11 Three state delay measurement
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