PDSP1601MC Datasheet, PDF (10/18 Pages) Mitel Networks Corporation – ALU and Barrel Shifter

PDSP1601 MC
ALU Control Instructions
Mnemonic ^{Op Code}
SBFOV
<18>
SBFU1
<19>
SBFU2
<1A>
SBFZE
OPONE
OPBYT
OPNIB
OPALT
<1B>
<1C>
<1D>
<1E>
<1F>
Function
The BFP flag is programmed to activate when an ALU operation causes an overflow of the
16 bit number range. This flag is logically the exclusive-or of the carry into and out of the
MSB of the ALU. For the most significant Byte this flag indicates that the result of an
arithmetic two's complement operation has overflowed into the sign bit. The output of the
ALU is forced to zero for the duration of this instruction.
The BFP flag is programmed to activate when an ALU operation comes within a factor of
two of causing an overflow of the 16 bit number range. For the most significant Byte this
flag indicates that the result of an arithmetic two's complement operation is within a factor
of two of overflowing into the sign bit. The output of the ALU is forced to zero for the duration
of this instruction.
The BFP flag is programmed to activate when an ALU operation comes within a factor of
four of causing an overflow of the 16 bit number range. For the most significant Byte this
flag indicates that the result of an arithmetic two's complement operation is within a factor
of four of overflowing into the sign bit. The output of the ALU is forced to zero for the duration
of this instruction.
The BFP flag is programmed to activate when an ALU operation causes a result of zero.
The output of the ALU is forced to zero for the duration of this instruction. During the
execution of this instruction the BFP flag will become active.
The ALU will output the binary value 0000000000000001, the MSB on the left.
The ALU will output the binary value 0000000011111111, the MSB on the left.
The ALU will output the binary value 0000000000001111, the MSB on the left.
The ALU will output the binary value 0101010101010101, the MSB on the left.
Barrel Shifter Instructions
Mnemonic ^{Op Code}
Function
LSRSV
<0>
The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by
the magnitude of the four bit number present in the SV register. The LSBs are discarded,
and the vacant MSBs are filled with zeros.
LSLSV
<1>
The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number present in the SV register. The MSBs are discarded, and
the vacant LSBs are filled with zeros.
BSRSV
<2>
The 16 bit input to the Barrel Shifter is rotated to the right shifted by the number of places
indicated by the magnitude of the four bit number present in the SV register. The LSBs that
exit the 16 bit field to the right, reappear in the vacant MSBs on the left.
BSLSV
<3>
The 16 bit input to the Barrel Shifter is rotated to the left shifted by the number of places
indicated by the magnitude of the four bit number present in the SV register. The MSBs
that exit the 16 bit field to the left, reappear in the vacant LSBs on the right.
LSRR1
<4>
The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by
the magnitude of the four bit number present in the R1 register. The LSBs are discarded,
and the vacant MSBs are filled with zeros.
LSLR1
<5>
The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number present in the R1 register. The MSBs are discarded, and
the vacant LSBs are filled with zeros.
LSRR2
<6>
The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated by
the magnitude of the four bit number present in the R2 register. The LSBs are discarded,
and the vacant MSBs are filled with zeros.
LSLR2
<7>
The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by the
magnitude of the four bit number present in the R2 register. The MSBs are discarded, and
the vacant LSBs are filled with zeros.
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