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MT93L16 Datasheet, PDF (1/27 Pages) Mitel Networks Corporation – CMOS Low-Voltage Acoustic Echo Canceller
CMOS MT93L16
Low-Voltage Acoustic Echo Canceller
Preliminary Information
Features
• Contains two echo cancellers: 112ms acoustic
echo canceller + 16ms line echo canceller
• Works with low cost voice codec. ITU-T G.711
or signed mag µ/A-Law, or linear 2’s comp
• Each port may operate in different format
• Advanced NLP design - full duplex speech with
no switched loss on audio paths
• Fast re-convergence time: tracks changing
echo environment quickly
• Adaptation algorithm converges even during
Double-Talk
• Designed for exceptional performance in high
background noise environments
• Provides protection against narrow-band signal
divergence
• Howling prevention stops uncontrolled
oscillation in high loop gain conditions
• Offset nulling of all PCM channels
• Serial micro-controller interface
• ST-BUS, GCI, or variable-rate SSI PCM
interfaces
• User gain control provided for speaker path
(-24dB to +21dB in 3dB steps)
DS5068
ISSUE3
July 1999
Ordering Information
MT93L16AQ
36 Pin QSOP
-40 °C to + 85 °C
• AGC on speaker path
• Handles up to 0 dB acoustic echo return loss
and 0dB line ERL
• Transparent data transfer and mute options
• 20 MHz master clock operation
• Low power mode during PCM Bypass
• Bootloadable for future factory software
upgrades
• 2.7V to 3.6V supply voltage; 5V-tolerant inputs
Applications
• Full duplex speaker-phone for digital telephone
• Echo cancellation for video conferencing
• Handsfree in automobile environment
• Full duplex speaker-phone for PC
Sin
MD1
MD2
Rout
µ/A-Law/
Linear
Offset
Null
NBSD
+
+
-
S1
Adaptive
Filter
R3
Limiter
ADV
NLP
S2
S3
CONTROL
Program
RAM
Program
ROM
Linear/
µ/A-Law
Micro
Interface
UNIT
Double
Talk
Detector
Adaptive
Filter
Howling
Controller
NBSD
R1
Linear/
µ/A-Law
R2
-24 -> +21dB
AGC
User
Gain
ADV
NLP
Limiter
-
+
+
Offset
Null
µ/A-Law/
Linear
VDD
VSS
RESET FORMAT ENA2
ENA1
LAW F0i BCLK/C4i MCLK
Figure 1 - Functional Block Diagram
Sout
DATA1
DATA2
SCLK
CS
Rin
1