B1005-BD_08 Datasheet, PDF (10/12 Pages) Mimix Broadband – 35.0-45.0 GHz GaAs MMIC

35.0-45.0 GHz GaAs MMIC
Buffer Amplifier
October 2008 - Rev 02-Oct-08
B1005-BD
App Note [1] Biasing - As shown in the bonding diagram, this device can be operated with all three stages in parallel, and can be
biased for low noise performance or high power performance. Low noise bias is nominally Vd=3.5V, Id=50mA. More controlled
performance will be obtained by separately biasing Vd1, Vd2 and Vd3 each at 3.5V, with Id1=9mA, Id2=16mA, Id3=25mA. Power bias
may be as high as Vd=4.5V, Id=154mA with all stages in parallel, or most controlled performance will be obtained by separately
biasing Vd1, Vd2 and Vd3 each at 4.5V, with Id1=28mA, Id2=42mA, Id3=84mA. It is also recommended to use active biasing to keep
the currents constant as the RF power and temperature vary; this gives the most reproducible results. Depending on the supply
voltage available and the power dissipation constraints, the bias circuit may be a single transistor or a low power operational
amplifier, with a low value resistor in series with the drain supply used to sense the current. The gate of the pHEMT is controlled to
maintain correct drain current and thus drain voltage. The typical gate voltage needed to do this is -0.4V. Typically the gate is
protected with Silicon diodes to limit the applied voltage. Also, make sure to sequence the applied voltage to ensure negative gate
bias is available before applying the positive drain supply.
App Note [2] Bias Arrangement -
For Parallel Stage Bias (Recommended for general applications) -- The same as Individual Stage Bias but all the drain or gate pad DC
bypass capacitors ( 100-200 pf ) can be combined. Additional DC bypass capacitance ( 0.01 uF) is also recommended to all DC or
combination (if gate or drains are tied together) of DC bias pads.
For Individual Stage Bias (Recommended for Saturated Applications) -- Each DC pad (Vd1,2,3 and Vg1,2,3) needs to have DC bypass
capacitance ( 100-200 pf ) as close to the device as possible. Additional DC bypass capacitance ( 0.01 uF) is also recommended.
MTTF Table
These numbers were calculated based on accelerated life test information and thermal model analysis received from the fabricating foundry.
Backplate
Temperature
55 deg Celsius
75 deg Celsius
95 deg Celsius
Channel
Temperature
82.9 deg Celsius
105.0 deg Celsius
126.8 deg Celsius
Rth
159.3° C/W
171.3° C/W
182.0° C/W
MTTF Hours
8.36E+10
5.38E+09
4.79E+08
FITs
1.20E-02
1.86E-01
2.09E+00
Bias Conditions: Vd1=Vd2=Vd3=3.5V, Id1=9 mA, Id2=16 mA, Id3=25 mA
Backplate
Temperature
55 deg Celsius
75 deg Celsius
95 deg Celsius
Channel
Temperature
157.3 deg Celsius
184.0 deg Celsius
210.1 deg Celsius
Rth
147.6° C/W
157.3° C/W
166.1° C/W
MTTF Hours
3.00E+07
3.07E+06
4.21E+05
FITs
3.34E+01
3.26E+02
2.37E+03
Bias Conditions: Vd1=Vd2=Vd3=4.5V, Id1=28 mA, Id2=42 mA, Id3=84 mA
Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099
Tel: [phone] Fax: [phone] mimixbroadband.com
Page 10 of 12
Characteristic Data and Specifications are subject to change without notice. ©2008 Mimix Broadband, Inc.
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