MYXN25Q256A13ESF Datasheet, PDF (18/31 Pages) Micross Components – SPI-compatible serial bus interface

is input on DQ0. A minimum de-selection time of ^tSHSL2 must come between the RE-
SET ENABLE and RESET MEMORY commands or a reset is not guaranteed. When these
two commands are executed and S# is driven HIGH, the device enters a power-on reset
condition. A time of ^tSHSL3 is required before the device can be re-selected by driving
S# LOW. It is recommended that
commands to initiate a reset.
the
device
ex_Sit X_eIP_rim_ao_lde_Nbe_Ofo_Rre
e_Fxe_lc_aut_sin_hg th_Mese_etw_mo _ory
If a reset is initiated while a WRITE, PROGRAM, or ERA^MSE^Yop^Xer^Nat²io⁵n i^Qs i²n p⁵r⁶og^Are¹ss³o^Er ^SF*
suspended, the operation is aborted and data may be corrupted.
*Advanced information. Subject to change without notice.
Figure 35: RES_FiE_gT_urE_eN₈A_{: F}B_iL_gE_ura_en₃d_5:R_RE_ES_SE_ET_T M_ENE_AM_BLO_ER_aY_ndCo_Rm_ESm_ETan_Md_{EMORY Command}
01234567
C
Reset enable
S#
01234567
Reset memory
DQ0
Note: 1. The number of lines and rate for transmission varies with extended, dual, or quad SPI.
9.2_{RESET Cond}R_iE_tS_ioE_nT_sConditions
All volatile loAckll vboitlsa,titlheelovcoklabtiliets,ctohnefigvuorlaattioilne creognisfitgeur,rathteionenrheagniscteedr, tvhoelaetilnehcaonncfeigdurvaotiloantilreegcoisntefri,guanrad- the
extended ad^td^ioreⁿss^rer^geⁱg^si^ts^et^re^,r^aaⁿr^de ^tr^he^ese^et^xt^to^ent^dhe^edp^ao^dw^de^rr^e-o^sn^{s r}r^ee^gsⁱe^st^ted^re^afa^reult^rec^so^en^td^toitio^thn^e. T^ph^oe^wep^ro^-w^oner-^ro^en^ser^te^ds^ee^ft^ac^uo^ltndition
depends on ^cus^oe_ratⁿt_ti^dn_ioig^tns^iorin^ne.gth^Tise^hteen_ro^p.n^ov^wol^ea^rt^-il^oeⁿco^ren^sfi^eg^tu^cra^otⁿio^dn^itrⁱe^ogⁿis^dte^er.^{pends on settings in the nonvolatile config-}
Reset is effective once bit 7 of the flag status register outputs 1 with at least one byte
10
ADDRESS MODE Operations: output. A RESET ENABLE command is not accepted in the cases of WRITE STATUS
REGISTER and WRITE NONVOLATILE CONFIGURATION REGISTER operations.
Enter and Exit 4-Byte Address Mode
Both ENTER 4-BYTE ADDRESS MODE and EXIT 4-BYTE ADDRESS MODE commands share the same
requirements.
To enter or exit the 4-byte address mode, the WRITE ENABLE command must be executed to set the write
enable latch bit to 1.
S# must be driven LOW. The command mus⁶t⁹be input on DQn. The effect of the command is immediate; after ^{PDF: 09005aef84752721}
n25q_512mb_1ce_3V_65nm.pdf - Rev. Q 11/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
the command has been executed, the write enable latch bit is cleared to 0.
The default address mode is three bytes, and the device returns to the default upon exiting the 4-byte
address mode.
MYXN25Q256A13ESF*
Revision 1.2 - 04/4/2016
18
Form #: CSI-D-685 Document 016