MYXN25Q256A13ESF Datasheet, PDF (17/31 Pages) Micross Components – SPI-compatible serial bus interface

Serial NOR Flash Memory
MYXN25Q256A13ESF*
Command
READ OTP ARRAY
PROGRAM OTP ARRAY
ENTER 4-BYTE ADDRESS MODE
EXIT 4-BYTE ADDRESS MODE
*Advanced information. Subject to change without notice.
Code Extended Dual I/O Quad I/O
ONE-TIME PROGRAMMABLE (OTP) Operations
4Bh
Yes
Yes
Yes
42h
Yes
Yes
Yes
4-BYTE ADDRESS MODE Operations
B7h
Yes
Yes
Yes
E9h
Yes
Yes
Yes
Data Bytes
1 to 64
1 to 64
0
0
Note: “Yes” in the protocol columns indicates that the command is supported and has the same functionality
and command sequence as other commands marked “Yes.”
9
RESET Operations
Table 6: Reset Command Set
Command
RESET ENABLE
RESET MEMORY
Command Code (Binary)
0110 0110
1001 1001
Command Code (Hex)
66
99
Address Bytes
0
0
9.1
RESET ENABLE and RESET MEMORY Command
To reset the device, the RESET ENABLE command must be followed by the RESET MEMORY command. To
execute each command, S# is driven LOW. The command code is input on DQ0. A minimum de-selection
time of ^tSHSL2 must come between the RESET ENABLE and RESET MEMORY commands or a reset is not
guaranteed. When these two commands are executed and S# is driven HIGH, the device enters a power-on
reset condition. A time of ^tSHSL3 is required before the device can be re-selected by driving S# LOW. It is
recommended that the device exit XIP mode before executing these two commands to initiate a reset.
If a reset is initiated while a WRITE, PROGRAM, or ERASE operation is in progress or suspended, the operation
is aborted and data may be corrupted.
MYXN25Q256A13ESF*
Revision 1.2 - 04/4/2016
17
Form #: CSI-D-685 Document 016