AS4SD32M16 Datasheet, PDF (10/52 Pages) Austin Semiconductor – 512Mb: 32 Meg x 16 SDRAM Synchronous DRAM Memory

SDRAM
AS4SD32M16
READs
READ bursts are initiated with a READ command, as
shown in Figure 5.
The starting column and bank addresses are provided with
the READ command, and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the
burst. For the generic READ commands used in the following
illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the
starting column address will be available following the CAS
latency after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge. Figure 6
shows general timing for each possible CAS latency setting.
Upon completion of a burst, assuming no other commands
have been initiated, the DQs will go High-Z. A full-page burst
will continue until terminated. (At the end of the page, it will
wrap to the start address and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-length
READ burst may be immediately followed by data from a
READ command. In either case, a continuous flow of data
can be maintained. The first data element from the new burst
follows either the last element of a complete burst or the last
desired data element of a longer burst that is being truncated.
The new READ command should be issued x cycles before
the clock edge at which the last desired data element is valid,
where x equals the CAS latency minus one. This is shown in
Figure 7 for CAS latencies of two and three; data element n+3
is either the last of a burst of four or the last desired of a longer
burst. The 512Mb SDRAM uses a pipelined architecture and
therefore does not require the 2n rule associated with a prefetch
architecture. A READ command can be initiated on any clock
cycle following a previous READ command. Full-speed ran-
dom read accesses can be performed to the same bank, as shown
in Figure 8, or each subsequent READ may be performed to
different bank.
FIGURE 5: READ Command
FIGURE 6: CAS Latency
CLK
CKE
CS\
RAS\
CAS\
WE\
A0-A9
A11, A12
A10
BA0, 1
AS4SD32M16
Rev. 2.0 10/13
10
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