JANSR2N2907AUB Datasheet, PDF (4/6 Pages) Microsemi Corporation – ABSOLUTE MAXIMUM RATINGS (TC = +25°C unless otherwise noted)

6 Lake Street, Lawrence, MA 01841
1-800-446-1158 / [phone] / Fax: [phone]
Website: http: //www.microsemi.com
TECHNICAL DATA SHEET
NOTES:
1. Dimensions are in inches.
2. Millimeters are given for general information only.
3. Dimension CH controls the overall package thickness. When a
window lid is used, dimension CH must increase by a minimum of
.010 inch (0.254 mm) and a maximum of .040 inch (1.020 mm).
4. The corner shape (square, notch, radius) may vary at the
manufacturer's option, from that shown on the drawing.
5. Dimensions LW2 minimum and L3 minimum and the appropriate
castellation length define an unobstructed three-dimensional space
traversing all of the ceramic layers in which a castellation was
designed. (Castellations are required on the bottom two layers,
optional on the top ceramic layer.) Dimension “LW2” maximum and
“L3” maximum define the maximum width and depth of the
castellation at any point on its surface. Measurement of these
dimensions may be made prior to solder dipping.
6. The co-planarity deviation of all terminal contact points, as defined
by the device seating plane, shall not exceed .006 inch (0.15mm) for
solder dipped leadless chip carriers.
7. In accordance with ASME Y14.5M, diameters are equivalent to φx
symbology.
Dimensions
Symbol
Inches
Millimeters Note
Min Max Min Max
BL .215 .225 5.46 5.71
BL2
.225
5.71
BW .145 .155 3.68 3.93
BW2
.155
3.93
CH .061 .075 1.55 1.90 3
L3
.003 .007 0.08 0.18
5
LH .029 .042 0.74 1.07
LL1 .032 .048 0.81 1.22
LL2 .072 .088 1.83 2.23
LS
.045 .055 1.14 1.39
LW .022 .028 0.56 0.71
LW2 .006 .022 0.15 0.56 5
Pin no.
1
2
3
4
Transistor Collector Emitter Base N/C
FIGURE 2. Physical dimensions, surface mount (UA version)
T4-LDS-0055 Rev. 4 (100247)
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