MT9V135C12STC Datasheet, PDF (8/17 Pages) Micron Technology – 1/4-Inch System-On-A-Chip (SOC) VGA NTSC/PAL CMOS Digital Image Sensor

Preliminary
MT9V135: SOC VGA Digital Image Sensor
Detailed Architecture Overview
Detailed Architecture Overview
Sensor Core
The sensor consists of a pixel array of 695 x 512, an analog readout chain, 10-bit ADC
with programmable gain and black offset, and timing and control, as illustrated in
Figure 6.
Figure 6: Sensor Core Block Diagram
Active Pixel
Sensor (APS)
Array
Control Register
Timing and Control
Communication
Bus
to IFP
Clock
Sync
Signals
Analog Processing
ADC
10-Bit Data
to IFP
There are 649 columns by 498 rows of optically-active pixels that include a pixel
boundary around the VGA (640 x 480) image to avoid boundary effects during color
interpolation and correction.
The one additional active column and two additional active rows are used to enable
horizontally and vertically mirrored readout to start on the same color pixel.
Figure 7 on page 9 illustrates the process of capturing the image. The original scene is
flipped and mirrored by the sensor optics. Sensor readout starts at the lower right hand
corner. The image is presented in true orientation by the output display.
PDF: 09005aef82c99cd/Source:09005aef824c99db
MT9V135_LDS_2.fm - Rev. B 3/07 EN
8
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