MT9V135C12STC Datasheet, PDF (7/17 Pages) Micron Technology – 1/4-Inch System-On-A-Chip (SOC) VGA NTSC/PAL CMOS Digital Image Sensor

Preliminary
MT9V135: SOC VGA Digital Image Sensor
Typical Connections
Table 4: Pin Descriptions (continued)
Pin
Assignment
27
26
6, 7, 8, 9, 10,
11, 12, 13
14
20
5, 4, 3, 2, 1, 48,
47, 46
44
45
42
41
43
35
33
31
39
38
29
15, 32, 37
28
30
16, 36
34
40
Name
PEDESTAL
LVDS_ENABLE
DIN[7:0]
Type
Input
Input
Input
Description
If “0” at reset: Does not add pedestal to composite video output.
If “1” at reset: Adds pedestal to composite video output.
Valid for NTSC only, pull low for PAL operation.
Active HIGH: Enables the LVDS output port. Must be HIGH if LVDS is
to be used.
External data input port selectable at video encoder input.
DIN_CLK
SDATA
DOUT[7:0]
DOUT_LSB0
DOUT_LSB1
FRAME_VALID
LINE_VALID
PIXCLK
DAC_POS
DAC_NEG
DAC_REF
LVDS_POS
LVDS_NEG
AGND
DGND
VAA
VAAPIX
VDD
VDDDAC
VDDPLL
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
Supply
DIN capture clock. (This clock must be synchronous to CLK_IN.)
Two-wire serial interface data I/O.
Pixel data output DOUT7 (most significant bit (MSB)), DOUT0 (least
significant bit (LSB)). Data output [9:2] in sensor stand-alone mode.
Sensor stand-alone mode output 0—typically left unconnected for
normal SOC operation.
Sensor stand-alone mode output 1—typically left unconnected for
normal SOC operation.
Active HIGH: FRAME_VALID; indicates active frame.
Active HIGH: LINE_VALID, DATA_VALID; indicates active pixel.
Pixel clock output.
Positive video DAC output in differential mode.
Video DAC output in single-ended mode.
Negative video DAC output in differential mode.
External reference resistor for video DAC.
LVDS positive output.
LVDS negative output.
Analog ground.
Digital ground.
Analog power: 2.5V–3.1V (2.8V nominal).
Pixel array analog power supply: 2.5V–3.1V (2.8V nominal).
Digital power: 2.5V-3.1V (2.8V nominal).
DAC power: 2.5V-3.1V (2.8V nominal).
LVDS PLL power: 2.5V-3.1V (2.8V nominal).
Notes:
1. ALL power pins (VDD/VDDDAC/VDDPLL/VAA/VAAPIX) must be connected to 2.8V
(nominal). Power pins cannot be floated.
2. ALL ground pins (AGND/DGND) must be connected to ground. Ground pins cannot be
floated.
3. Inputs are not tolerant to signal voltages above 3.1V.
4. All unused inputs must be tied to GND or VDD.
5. VAA and VAAPIX must be tied to the same potential for proper operation.
PDF: 09005aef82c99cd/Source:09005aef824c99db
MT9V135_LDS_2.fm - Rev. B 3/07 EN
7
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