MT58L256V36F Datasheet, PDF (8/27 Pages) Micron Technology – 8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM

8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH SYNCBURST SRAM
TQFP PIN DESCRIPTIONS (CONTINUED)
x18
x32/x36 SYMBOL TYPE
DESCRIPTION
84
84
ADSP# Input Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
31
31
MODE Input Mode: This input selects the burst sequence. A LOW on this pin
selects “linear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating.
64
64
ZZ
Input Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
(a) 58, 59, (a) 52, 53,
62, 63, 68, 69, 56-59, 62, 63
72, 73
(b) 8, 9, 12, (b) 68, 69,
13, 18, 19, 72-75, 78, 79
22, 23
(c) 2, 3, 6-9,
12, 13
(d) 18, 19,
22-25, 28, 29
DQa
DQb
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte “b”
Output is DQb pins. For the x32 and x36 versions, Byte “a” is DQa pins;
Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins.
Input data must meet setup and hold times around the rising edge
of CLK.
DQc
DQd
74
51
NC/DQPa NC/ No Connect/Parity Data I/Os: On the x32 version, these pins are No
24
80
NC/DQPb I/O Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”
–
1
NC/DQPc
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
–
30
NC/DQPd
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
15, 41, 65, 91 15, 41, 65, 91 VDD Supply Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
4, 11, 20, 27, 4, 11, 20, 27, VDDQ Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
54, 61, 70, 77 54, 61, 70, 77
Operating Conditions for range.
5, 10, 14, 17, 5, 10, 14, 17, VSS Supply Ground: GND.
21, 26, 40, 55, 21, 26, 40, 55,
60, 67, 71, 60, 67, 71,
76, 90
76, 90
38, 39
38, 39
DNU
– Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1-3, 6, 7, 16,
25, 28-30,
51-53, 56, 57,
66, 75, 78, 79,
95, 96
16, 66
NC
– No Connect: These signals are not internally connected and may be
connected to ground to improve package heat dissipation.
42
42
NF
43 (T Version) 43 (T Version)
– No Function: These pins are internally connected to the die and
have the capacitance of an input pin. It is allowable to leave these
pins unconnected or driven by signals. On the S Version, pin 42 is
reserved as an address upgrade pin for the 16Mb SyncBurst SRAM.
8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM
MT58L512L18F_2.p65 – Rev. 7/00
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