MT58L256V36F Datasheet, PDF (7/27 Pages) Micron Technology – 8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM

8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH SYNCBURST SRAM
TQFP PIN DESCRIPTIONS
x18
x32/x36 SYMBOL
37
37
SA0
36
36
SA1
32-35, 44-50, 32-35, 44-50, SA
80-82, 99, 81, 82, 99,
100
100
92 (T Version) 92 (T Version)
43 (S Version) 43 (S Version)
93
93
BWa#
94
94
BWb#
–
95
BWc#
–
96
BWd#
87
87
BWE#
88
88
GW#
89
89
CLK
98
98
CE#
92 (S Version) 92 (S Version) CE2#
97
97
CE2
86
86
OE#
83
83
ADV#
85
85
ADSC#
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK. Two
different pinouts are available for the TQFP package.
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Clock: CLK registers address, data, chip enable, byte write enables
and burst control inputs on its rising edge. All synchronous inputs
must meet setup and hold times around the clock’s rising edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded. CE2# is only available on the S Version.
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on this pin effectively causes
wait states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM
MT58L512L18F_2.p65 – Rev. 7/00
7
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©2000, Micron Technology, Inc.