MT58L256V36F Datasheet, PDF (10/27 Pages) Micron Technology – 8Mb: 512K x 18, 256K x 32/36 FLOW-THROUGH SYNCBURST SRAM

8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH SYNCBURST SRAM
FBGA PIN DESCRIPTIONS
x18
x32/x36 SYMBOL
6R
6R
SA0
6P
6P
SA1
2A, 2B, 3P, 2A, 2B, 3P,
SA
3R, 4P, 4R, 3R, 4P, 4R,
8P, 8R, 9P, 9R, 8P, 8R, 9P,
10A, 10B, 10P, 9R, 10A, 10B,
10R, 11A, 11P, 10P, 10R, 11P,
11R
11R
5B
5B
BWa#
4A
5A
BWb#
–
4A
BWc#
–
4B
BWd#
7A
7A
BWE#
7B
7B
GW#
6B
6B
CLK
3A
3A
CE#
6A
6A
CE2#
11H
11H
ZZ
3B
3B
CE2
8B
8B
OE#(G#)
TYPE
DESCRIPTION
Input Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
Input
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For
the x32 and x36 versions, BWa# controls DQas and DQPa; BWb#
controls DQbs and DQPb; BWc# controls DQc’s and DQPc; BWd#
controls DQds and DQPd. Parity is only available on the x18 and x36
versions.
Input Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Input
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Input
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
Input Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
Input Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
(continued on next page)
8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM
MT58L512L18F_2.p65 – Rev. 7/00
10
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©2000, Micron Technology, Inc.