MT41J64M16JT Datasheet, PDF (79/214 Pages) Micron Technology – MT41J256M4 – 32 Meg x 4 x 8 banks

Electrical Characteristics and AC Operating Conditions
Table 56: Electrical Characteristics and AC Operating Conditions
Notes 1–8 apply to the entire table
Parameter
Clock period average: T_C ≤ 85°C
DLL disable mode
T_C = >85°C to 95°C
Clock period average: DLL enable mode
High pulse width average
Low pulse width average
Clock period jitter
DLL locked
DLL locking
Clock absolute period
Clock absolute high pulse width
Symbol
t_CK
(DLL_DIS)
t_{CK (AVG)}
t_{CH (AVG)}
t_{CL (AVG)}
t_JITper
t_JITper,lck
t_{CK (ABS)}
t_{CH (ABS)}
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Min Max Min Max Min Max Min Max
Clock Timing
8
7800
8
7800
8
7800
8
7800
8
3900
8
3900
8
3900
8
3900
See Speed Bin Tables (page 74) for ^tCK range allowed
0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53
0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53
–100 100
–90
90
–80
80
–70
70
–90
90
–80
80
–70
70
–60
60
MIN = ^tCK (AVG) MIN + ^tJITper MIN; MAX = ^tCK (AVG) MAX + ^tJITper
MAX
0.43
–
0.43
–
0.43
–
0.43
–
Clock absolute low pulse width
t_{CL (ABS) 0.43}
–
0.43
–
0.43
–
0.43
–
Cycle-to-cycle jitter
DLL locked
DLL locking
Cumulative error across 2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
8 cycles
9 cycles
10 cycles
11 cycles
12 cycles
n = 13, 14 . . . 49, 50
cycles
t_JITcc
t_JITcc,lck
t_ERR2per
t_ERR3per
t_ERR4per
t_ERR5per
t_ERR6per
t_ERR7per
t_ERR8per
t_ERR9per
t_ERR10per
t_ERR11per
t_ERR12per
t_ERRnper
200
180
160
140
180
160
140
120
–147 147 –132 132 –118 118 –103 103
–175 175 –157 157 –140 140 –122 122
–194 194 –175 175 –155 155 –136 136
–209 209 –188 188 –168 168 –147 147
–222 222 –200 200 –177 177 –155 155
–232 232 –209 209 –186 186 –163 163
–241 241 –217 217 –193 193 –169 169
–249 249 –224 224 –200 200 –175 175
–257 257 –231 231 –205 205 –180 180
–263 263 –237 237 –210 210 –184 184
–269 269 –242 242 –215 215 –188 188
t_{ERRnper MIN = (1 + 0.68ln[n]) ×} t_{JITper MIN}
t_{ERRnper MAX = (1 + 0.68ln[n]) ×} t_{JITper MAX}
Unit Notes
ns 9, 42
ns
42
ns 10, 11
CK
12
CK
12
ps
13
ps
13
ps
t_CK
14
(AVG)
t_CK
15
(AVG)
ps
16
ps
16
ps
17
ps
17
ps
17
ps
17
ps
17
ps
17
ps
17
ps
17
ps
17
ps
17
ps
17
ps
17