MT41J64M16JT Datasheet, PDF (156/214 Pages) Micron Technology – MT41J256M4 – 32 Meg x 4 x 8 banks

1Gb: x4, x8, x16 DDR3 SDRAM
ZQ CALIBRATION Operation
ZQ CALIBRATION Operation
The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (R_ON)
and ODT values (R_TT) over process, voltage, and temperature, provided a dedicated
240Ω (±1%) external resistor is connected from the DRAM’s ZQ ball to V_SSQ.
DDR3 SDRAM require a longer time to calibrate R_ON and ODT at power-up initialization
and self refresh exit, and a relatively shorter time to perform periodic calibrations.
DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQCL and ZQCS. An example
of ZQ calibration timing is shown below.
All banks must be precharged and ^tRP must be met before ZQCL or ZQCS commands
can be issued to the DRAM. No other activities (other than issuing another ZQCL or
ZQCS command) can be performed on the DRAM channel by the controller for the du-
ration of ^tZQinit or ^tZQoper. The quiet time on the DRAM channel helps accurately cali-
brate R_ON and ODT. After DRAM calibration is achieved, the DRAM should disable the
ZQ ball’s current consumption path to reduce power.
ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time.
Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.
In dual-rank systems that share the ZQ resistor between devices, the controller must not
enable overlap of ^tZQinit, ^tZQoper, or ^tZQCS between ranks.
Figure 65: ZQ CALIBRATION Timing (ZQCL and ZQCS)
CK#
T0
CK
Command ZQCL
Address
A10
CKE 1
ODT 2
DQ 3
T1
Ta0
Ta1
NOP
NOP
NOP
High-Z
t_{ZQinit or} t_ZQoper
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Valid
Valid
ZQCS
Valid
Valid
Valid
Valid
Valid
Valid
1
Valid
Valid
2
Activities
3
NOP
NOP
High-Z
t_ZQCS
NOP
Tc2
Valid
Valid
Valid
Valid
Valid
Activ-
ities
Indicates break
in time scale
Don’t Care
Notes: 1. CKE must be continuously registered HIGH during the calibration procedure.
2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure.
3. All devices connected to the DQ bus should be High-Z during calibration.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
156
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