MT41J64M16JT Datasheet, PDF (14/214 Pages) Micron Technology – MT41J256M4 – 32 Meg x 4 x 8 banks

1Gb: x4, x8, x16 DDR3 SDRAM
Functional Block Diagrams
Functional Block Diagrams
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
Figure 3: 256 Meg x 4 Functional Block Diagram
ODT
ZQ
RZQ RESET#
CKE
V_{SSQ A12}
CK, CK#
CS#
RAS#
CAS#
WE#
Control
logic
Mode registers
16
A[13:0]
BA[2:0]
17
Address
register
ZQCL, ZQCS
ZQ CAL
To pull-up/pull-down
networks
ODT
control
BC4 (burst chop)
OTF
Refresh
counter ¹⁴
Row-
14
address
MUX
14
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
row-
address
latch
and
decoder
16,384
Bank 0
memory
array
(16,384 x 256 x 32)
Sense amplifiers
8,192
3
Bank
control
logic
3
I/O gating
DM mask logic
256
(x32)
Column
decoder
Column-
8
11
address
counter/
latch
3
Columns 0, 1, and 2
Columns 0, 1, and 2
READ
32
FIFO
4
and
data
MUX
CK, CK#
DLL
READ
drivers
32
BC4
BC4
OTF
DM
WRITE
32
Data
4
drivers
interface
Data
and
input
logic
CK, CK#
Column 2
(select upper or
lower nibble for BC4)
V_DDQ/2
R_TT,nom R_TT(WR)
sw1
sw2
DQ[3:0]
DQS, DQS#
(1 . . . 4)
DQ[3:0]
V_DDQ/2
R_TT,nom R_TT(WR)
sw1
sw2
(1, 2)
V_DDQ/2
R_TT,nom
sw1
R_TT(WR)
sw2
DQS, DQS#
DM
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
14
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