PC28F640P33BF60A Datasheet, PDF (69/88 Pages) Micron Technology – Numonyx® P33-65nm Flash Memory

P33-65nm SBC
Table 39: Partition Region 1 Information (Sheet 2 of 2)
Offs e t⁽¹⁾
See table below
P = 10Ah
De s cr iption
Addre s s
Bottom Top
(Optional flash features and com m ands)
Len Bot
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(P+2C)h (P+2C)h Partition Region 1 Erase Block Type 1 Information
4 136: 136:
(P+2D)h (P+2D)h
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
137: 137:
(P+2E)h (P+2E)h
bits 16–31 = z, region erase block(s) size are z x 256 bytes
138: 138:
(P+2F)h (P+2F)h
139: 139:
(P+30)h (P+30)h Partition 1 (Erase Block Type 1)
2 13A: 13A:
(P+31)h (P+31)h Block erase cycles x 1000
13B: 13B:
(P+32)h (P+32)h Partition 1 (erase block Type 1) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
1 13C: 13C:
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+33)h (P+33)h Partition 1 (erase block Type 1) page mode and synchronous mode capabilities
defined in Table 10.
1 13D: 13D:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Partition Region 1 (Erase Block Type 1) Programming Region Information
6
(P+34)h (P+34)h
bits 0–7 = x, 2^x = Programming Region aligned size (bytes)
13E: 13E:
(P+35)h (P+35)h
bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
13F: 13F:
(P+36)h (P+36)h
bits 16–23 = y = Control Mode valid size in bytes
140: 140:
(P+37)h (P+37)h
bits 24-31 = Reserved
141: 141:
(P+38)h (P+38)h
bits 32-39 = z = Control Mode invalid size in bytes
142: 142:
(P+39)h (P+39)h
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
143: 143:
(P+3A)h (P+3A)h Partition Region 1 Erase Block Type 2 Information
4 144: 144:
(P+3B)h (P+3B)h
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
145: 145:
(P+3C)h (P+3C)h
bits 16–31 = z, region erase block(s) size are z x 256 bytes
146: 146:
(P+3D)h (P+3D)h
147: 147:
(P+3E)h (P+3E)h Partition 1 (Erase Block Type 2)
2 148: 148:
(P+3F)h (P+3F)h Block erase cycles x 1000
149: 149:
(P+40)h (P+40)h Partition 1 (erase block Type 2) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
1 14A: 14A:
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+41)h (P+41)h Partition 1 (erase block Type 2) page mode and synchronous mode capabilities
defined in Table 10.
1 14B: 14B:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitte
(P+42)h
(P+43)h
(P+44)h
(P+45)h
(P+46)h
(P+47)h
Partition Region 1 (Erase Block Type 2) Programming Region Information
6
(P+42)h
bits 0–7 = x, 2^x = Programming Region aligned size (bytes)
(P+43)h
bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
(P+44)h
bits 16–23 = y = Control Mode valid size in bytes
(P+45)h
bits 24-31 = Reserved
(P+46)h
bits 32-39 = z = Control Mode invalid size in bytes
(P+47)h
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
14C:
14D:
14E:
14F:
150:
151:
14C:
14D:
14E:
14F:
150:
151:
Datasheet
69
Jul 2011
Order Number:208034-04