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| MT48LC4M32B2P-7 Datasheet, PDF (65/80 Pages) Micron Technology – SDR SDRAM MT48LC4M32B2 – 1 Meg x 32 x 4 Banks | |||
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128Mb: x32 SDRAM
PRECHARGE Operation
Figure 38: READ Without Auto Precharge
T0
CLK
T1
tCK
tCKS tCKH
CKE
tCMS tCMH
Command
ACTIVE
NOP
DQM
tAS tAH
T2
tCL
tCH
READ
tCMS tCMH
Address
Row
Column m
A10
BA0, BA1
tAS tAH
Row
tAS tAH
Bank
Disable auto precharge
Bank
T3
NOP
DQ
tRCD
tRAS
tRC
CL = 2
tAC
tLZ
T4
NOP
tAC
tOH
DOUT
T5
T6
T7
NOP
PRECHARGE
NOP
tAC
tOH
DOUT
All banks
Single bank
Bank(s)
tAC
tOH
DOUT
tRP
tOH
DOUT
tHZ
T8
ACTIVE
Row
Row
Bank
Donât Care
Undefined
Note: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRE-
CHARGE.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. P 9/11 EN
65
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2001 Micron Technology, Inc. All rights reserved.
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