MT48LC8M32B2 Datasheet, PDF (48/55 Pages) Micron Technology – SYNCHRONOUS DRAM

SINGLE WRITE
T0
T1
T2
T3
T4
T5
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
PRECHARGE
NOP
DQM /
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
tCMS tCMH
COLUMN m³
DISABLE AUTO PRECHARGE
BANK
ALL BANKS
SINGLE BANK
BANK
tDS tDH
DQ
DIN m
tRCD
t _WR ²
tRP
tRAS
tRC
PRELIMINARY
256Mb: x32
SDRAM
T6
ACTIVE
ROW
ROW
BANK
DON’T CARE
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. ^tWR is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. A9 and A11 = “Don’t Care.”
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
48
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.