MT48LC8M32B2 Datasheet, PDF (41/55 Pages) Micron Technology – SYNCHRONOUS DRAM

PRELIMINARY
256Mb: x32
SDRAM
T0
CLK
tCK
CKE
tCKS tCKH
tCMS tCMH
COMMAND _PRECHARGE
DQM 0-3
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
tAS tAH
BA0, BA1
BANK(S)
High-Z
DQ
Precharge all
active banks
T1
tCH
SELF REFRESH MODE
T2
tCL
tCKS
((
))
((
> tRAS ^{) )}
Tn + 1
((
))
( ( ^{To + 1}
))
((
))
((
))
((
))
tCKS
NOP
((
AUTO
))
REFRESH
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
NOP _{( (}
))
((
))
((
))
((
))
((
))
((
))
((
))
((
((
))
))
((
((
))
))
((
((
))
))
tRP
tXSR
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
CLK stable prior to exiting
self refresh mode
To + 2
AUTO
REFRESH
DON’T CARE
UNDEFINED
09005aef80cd8e48
256MbSDRAMx32.p65 – Rev. B; Pub. 03/04
41
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©2003 Micron Technology, Inc.