MT9M111 Datasheet, PDF (42/61 Pages) Micron Technology – 1/3-INCH SOC MEGAPIXEL CMOS DIGITAL IMAGE SENSOR

PRELIMINARY
MT9M111
SOC MEGAPIXEL DIGITAL IMAGE SENSOR
Table 12: Sensor Core Register Descriptions (continued)
BIT FIELD
DESCRIPTION
DEFAULT SYNCED TO BAD READ/
(HEX) FRAME START FRAME WRITE
Bit 5
0: Normal readout.
0x0
Column Skip 4x 1: Readout two columns, and then skip six columns (as with
rows).
Bit 4
0: Normal readout.
0x0
Row Skip 4x 1:Readout two rows, and then skip six rows (i.e., row 8, row 9,
row 16, row 17…).
Bit 3
When read mode Context B is selected (bit 3, Reg0x0C8 = 1):
0x0
Column Skip 2x 0: Normal readout.
—Context B 1: Readout two columns, and then skip two columns (as with
rows).
Bit 2
When read mode Context B is selected (bit 3, Reg0x0C8 = 1):
0x0
Row Skip 2x— 0: Normal readout.
Context B
1: Readout two rows, then skip two rows (i.e., row 8, row 9,
row 12, row 13…).
Bit 1
Readout columns from right to left (mirrored). When set,
0x0
Mirror Columns column readout starts from column (Col Start + Col Size) and
continues down to (Col Start + 1). When clear, readout starts at
Col Start and continues to (Col Start + Col Size - 1). This ensures
that the starting color is maintained.
Bit 0
Readout rows from bottom to top (upside down). When set,
0x0
Mirror Rows row readout starts from row (Row Start + Row Size) and
continues down to (Row Start + 1). When clear, readout starts
at Row Start and continues to (Row Start + Row Size - 1). This
ensures that the starting color is maintained.
Y
YM
W
Y
YM
W
Y
YM
W
Y
YM
W
Y
YM
W
Y
YM
W
R33:0—0X021 - READ MODE—CONTEXT A
Bit 10
When read mode Context A is selected (bit 3, Reg0x0C8 = 0):
0x1
Power Readout 0: Full-power readout mode, maximum readout speed.
Mode—
1: Low-power readout mode. Maximum readout frequency is
Context A
now half of the master clock, and the pixel clock is
automatically adjusted as described for the pixel clock speed
register.
Bit 3
When read mode Context A is selected (bit 3, Reg0x0C8 = 0):
0x1
Column Skip 2x 0: Normal readout.
—Context A 1: Readout two columns, and then skip two columns (as with
rows).
Bit 2
When read mode Context A is selected (bit 3, Reg0x0C8 = 0):
0x1
Row Skip 2x— 0: Normal readout.
Context A
1: Readout two rows, and then skip two rows (i.e., row 8, row
9, row 12, row 13…).
Y
YM
W
Y
YM
W
Y
YM
W
R35:0—0X023 - FLASH CONTROL
Bit 15
Read-only bit that indicates whether the FLASH_STROBE pin is 0x0
0
0
R
Flash Strobe enabled.
Bit 14
Reserved.
—
—
—
—
Bit 13
Enable Xenon flash. When set, the FLASH_STROBE output pin 0x0
Y
N
W
Xenon Flash is pulsed HIGH for the programmed period during vertical
blanking. This is achieved by keeping the integration time
equal to one frame and the pulse width less than the vertical
blanking time.
Bits 12:11
Delay of the flash pulse measured in frames.
Frame Delay
0x0
N
N
W
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MT9M111__SOC1310__2.fm - Rev. C 10/04 EN
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