MT49H16M18C Datasheet, PDF (41/44 Pages) Micron Technology – 288Mb SIO REDUCED LATENCY(RLDRAM II)

16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Absolute Maximum Ratings*
Storage Temperature . . . . . . . . . . . . . . . .-55°C to +150°C
I/O Voltage . . . . . . . . . . . . . . . . . . . . -0.3V to VDDQ + 0.3V
Voltage on VEXT Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.8V
Voltage on VDD Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.1V
Voltage on VDDQ Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.1V
Junction Temperature** . . . . . . . . . . . . . . . . . . . . . . .110°C
*Stresses greater than those listed may cause per-
manent damage to the device. This is a stress rating
only, and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
**Junction temperature depends upon package
type, cycle time, loading, ambient temperature, and
airflow.
Table 19: DC Electrical Characteristics and Operating Conditions
(+0°C ≤ T_C ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted)
DESCRIPTION
Supply Voltage
Supply Voltage
Isolated Output Buffer Supply
Reference Voltage
Termination Voltage
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Output High Current
Output Low Current
Clock Input Leakage Current
Input Leakage Current
Output Leakage Current
Reference Voltage Current
CONDITIONS
VOH = VDDQ/2
VOL = VDDQ/2
0V ≤ VIN ≤ VDD
0V ≤ VIN ≤ VDD
0V ≤ VIN ≤ VDDQ
SYMBOL
VEXT
VDD
VDDQ
VREF
VTT
VIH
VIL
IOH
IOL
ILC
ILI
ILO
IREF
MIN
MAX
2.38
2.63
1.7
1.9
1.4
Vdd
0.49 X VDDQ 0.51 X VDDQ
0.95 X VREF 1.05 X VREF
VREF + 0.1 VDDQ + 0.3
VSSQ - 0.3 VREF - 0.1
(VDDQ/2) / (VDDQ/2) /
(1.15 X RQ/5) (0.85 X RQ/5)
(VDDQ/2) / (VDDQ/2) /
(1.15 X RQ/5) (0.85 X RQ/5)
-5
5
-5
5
-5
5
-5
5
UNITS
V
V
V
V
V
V
V
mA
mA
µA
µA
µA
µA
NOTES
1
1, 4
1, 4, 5
1–3, 8
9, 10
1, 4
1, 4
6, 7, 11
6, 7, 11
NOTE:
1. All voltages referenced to VSS (GND).
2. Typically the value of VREF is expect to be 0.5 x VDDQ of the transmitting device. VREF is expected to track variations in
VDDQ.
3. Peak-to-peak AC noise on VREF must not exceed ±2% VREF(dc).
4. Overshoot: VIH(AC) ≤ VDD + 0.7V for t ≤ ^tCK/2.
Undershoot: VIL(AC) ≥ -0.5V for t ≤ ^tCK/2.
During normal operation, VDDQ must not exceed VDD.
Control input signals may not have pulse widths less than ^tCK/2 or operate at frequencies exceeding ^tCK (MAX).
5. VDDQ can be set to a nominal 1.5V + 0.1V or 1.8V + 0.1V supply
6. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from the device, IOL flows into the
device.
7. If MRS bit A8 is 0, use RQ = 250Ω in the equation in lieu of presence of an external impedance matched resistor.
8. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-
peak noise (non-common mode) on VREF may not exceed ±2% of the DC value. Thus, from VDDQ/2, VREF is allowed
±2%VDDQ/2 for DC error and an additional ±2%VDDQ/2 for AC noise. This measurement is to be taken at the nearest
VREF bypass capacitor.
9. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
10. On-die termination may be selected using mode register bit 9 (see Figure 10 on page 16). A resistance RTT from each
data input signal to the nearest VTT can be enabled. RTT = 150Ω (± 10%) at 70°C T_C.
11. For VOL and VOH, refer to the Spice Model fro the RLDRAM II Command Driver.
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
41
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