MT49H16M18C Datasheet, PDF (1/44 Pages) Micron Technology – 288Mb SIO REDUCED LATENCY(RLDRAM II)

16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
288Mb SIO REDUCED MT49H16M18C
MT49H32M9C
LATENCY (RLDRAM II)
Features
• 288Mb
• 400 MHz DDR operation (800 Mb/s/pin data rate)
• Organization
• 16 Meg x 18, 32 Meg x 9 Separate I/O
• 8 banks
• Cyclic bank switching for maximum bandwidth
• Reduced cycle time (20ns at 400 MHz)
• Nonmultiplexed addresses (address multiplexing
option available)
• SRAM-type interface
• Read latency (RL), row cycle time, and burst
sequence length
• Balanced READ and WRITE latencies in order to
optimize data bus utilization
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Differential input data clocks (DKx, DKx#)
• On-chip DLL generates CK edge-aligned data and
output data clock signals
• Data valid signal (QVLD)
• 32ms refresh (8K refresh for each bank; 64k refresh
command must be issued in total each 32ms)
• 144-ball FBGA package
• HSTL I/O (1.5V or 1.8V nominal)
• 25Ω–60Ω matched impedance outputs
• 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
• On-die termination (ODT) RTT
Options
• Clock Cycle Timing
2.5ns (400 MHz)
3.3ns (300 MHz)
5ns (200 MHz)
• Configuration
16 Meg x 18
32 Meg x 9
• Package
144-ball FBGA
(11mm x 18.5mm)
Marking
-25
-33
-5
MT49H16M18CFM
MT49H32M9CFM
FM
BM (lead-free)¹
NOTE: 1. Contact Micron for availability of lead-free
products.
Figure 1: 144-Ball FBGA
Table 1: Valid Part Numbers
PART NUMBER
MT49H16M18CFM-xx
MT49H32M9CFM-xx
DESCRIPTION
16 Meg x 18 RLDRAM II
32 Meg x 9 RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_1.fm - Rev. F 11/04 EN
1
©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.