MT49H16M18C Datasheet, PDF (16/44 Pages) Micron Technology – 288Mb SIO REDUCED LATENCY(RLDRAM II)

16 MEG x 18, 32 MEG x 9
2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II
Mode Register Set Command (MRS)
The mode register stores the data for controlling the
operating modes of the memory. It programs the
RLDRAM configuration, burst length, test mode, and
I/O options. During a MRS command, the address
inputs A(17:0) are sampled and stored in the mode reg-
ister. ^tMRSC must be met before any command can be
issued to the RLDRAM. The mode register may be set
at any time during device operation. However, any
pending operations are not guaranteed to successfully
complete. See the RLDRAM II design guide for more
details.
Figure 8: Mode Register Set Timing
CK#
CK
Figure 9: Mode Register Set
CK#
CK
CS#
WE#
REF#
A(17:0)
COD
A(20:18)
CMD MRS
NOP
NOP
AC
BA(2:0)
t_MRSC
DON’T CARE
DON’T CARE
NOTE:
MRS: MRS command and AC: any command.
NOTE:
COD: code to be loaded into the register.
Figure 10: Mode Register Bit Map
A(17:10)
A9
A8
A7
A6
A5
A4
A3
Reserved¹
On-Die
Termination
Impedance
Matching
DLL Reset
Unused
Address
Mux
Burst Length
On-Die
Termination
A9 Termination
DLL Reset
A7
DLL Reset
Burst Length
A4 A3
BL
0 Disabled (default)
1
Enabled
0 DLL reset (default)
1 DLL enabled
00
01
10
Impedance
Matching
A8
Resistor
11
Address Mux
A5 Address Mux
0
internal 50Ω³
(default)
1
external
0 nonmultiplexed
(default)
1 address multiplexed
2 (default)
4
8²
not valid
NOTE:
1. Bits A(17:10) must be set to zero.
2. BL = 8 is not available for configuration 1.
3. ±15% temperature variation.
A2
A1
A0
Configuration
Configuration
A2 A1 A0
RLDRAM
Configuration
000
001
010
011
100
101
110
111
1² (default)
1²
2
3
reserved
reserved
reserved
reserved
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
16
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