MT48LC1M16A1S Datasheet, PDF (41/51 Pages) Micron Technology – SYNCHRONOUS DRAM

READ – WITH AUTO PRECHARGE ¹
T0
CLK
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
T1
tCK
NOP
DQM³
A0-A9
tAS tAH
ROW
T2
tCL
tCH
READ
tCMS tCMH
COLUMN m
(A0 - A7)²
T3
NOP
tAS tAH
A10
ROW
tAS tAH
BA
BANK
ENABLE AUTO PRECHARGE
BANK
DQ
tRCD
tRAS
tRC
tAC
tLZ
CAS Latency
T4
T5
T6
NOP
NOP
NOP
tAC
tOH
DOUT m
tAC
tOH
DOUT m + 1
tAC
tOH
DOUT m + 2
tRP
16Mb: x16
SDRAM
T7
T8
NOP
ACTIVE
ROW
ROW
tOH
DOUTm + 3
tHZ
BANK
TIMING PARAMETERS
SYMBOL*
t_{AC (3)}
t_{AC (2)}
t_{AC (1)}
t_AH
t_AS
t_CH
t_CL
t_{CK (3)}
t_{CK (2)}
t_{CK (1)}
t_CKH
t_CKS
-6
MIN MAX
5.5
8
18
1
2
2.5
2.5
6
8
20
1
2
-7
MIN MAX
5.5
8.5
22
1
2
2.75
2.75
7
10
25
1
2
-8A
MIN MAX
6
9
22
1
2
3
3
8
13
25
1
2
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DON’T CARE
UNDEFINED
SYMBOL*
t_CMH
t_CMS
t_{HZ (3)}
t_{HZ (2)}
t_{HZ (1)}
t_LZ
t_OH
t_RAS
t_RC
t_RCD
t_RP
-6
MIN MAX
1
2
5.5
8
18
1
2
42 120,000
60
18
18
-7
MIN MAX
1
2
5.5
8.5
22
1
2
42 120,000
70
20
21
-8A
MIN MAX UNITS
1
ns
2
ns
6
ns
9
ns
22
ns
1
ns
2.5
ns
48 120,000 ns
80
ns
24
ns
24
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. A8 and A9 = “Don’t Care.”
3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
16Mb: x16 SDRAM
16MSDRAMx16.p65 – Rev. 8/99
41
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©1999, Micron Technology, Inc.