MT48LC1M16A1S Datasheet, PDF (1/51 Pages) Micron Technology – SYNCHRONOUS DRAM

SYNCHRONOUS
DRAM
16Mb: x16
SDRAM
MT48LC1M16A1 S - 512K x 16 x 2 banks
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/datasheets/sdramds.html
FEATURES
• PC100 functionality
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
1 Meg x 16 - 512K x 16 x 2 banks architecture with
11 row, 8 column addresses per bank
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge Mode, includes CONCURRENT
AUTO PRECHARGE
• Self Refresh and Adaptable Auto Refresh Modes
- 32ms, 2,048-cycle refresh or
- 64ms, 2,048-cycle refresh or
- 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2 and 3
OPTIONS
• Configuration
1 Meg x 16 (512K x 16 x 2 banks)
MARKING
1M16A1
• Plastic Package - OCPL*
50-pin TSOP (400 mil)
TG
• Timing (Cycle Time)
6ns (166 MHz)
-6
7ns (143 MHz)
-7
8ns (125 MHz)
-8A
• Refresh
2K or 4K with Self Refresh Mode at 64ms S
Part Number Example:
MT48LC1M16A1TG-7S
KEY TIMING PARAMETERS
SPEED
-6
-7
-8A
CLOCK
166 MHz
143 MHz
125 MHz
ACCESS TIME
CL = 3**
5.5ns
5.5ns
6ns
SETUP
2ns
2ns
2ns
HOLD
1ns
1ns
1ns
*Off-center parting line
**CL = CAS (READ) latency
PIN ASSIGNMENT (Top View)
50-Pin TSOP
VDD
1
DQ0
2
DQ1
3
VssQ
4
DQ2
5
DQ3
6
VDDQ
7
DQ4
8
DQ5
9
VssQ
10
DQ6
11
DQ7
12
VDDQ
13
DQML
14
WE#
15
CAS#
16
RAS#
17
CS#
18
BA
19
A10
20
A0
21
A1
22
A2
23
A3
24
VDD
25
50
Vss
49
DQ15
48
DQ14
47
VssQ
46
DQ13
45
DQ12
44
VDDQ
43
DQ11
42
DQ10
41
VssQ
40
DQ9
39
DQ8
38
VDDQ
37
NC
36
DQMH
35
CLK
34
CKE
33
NC
32
A9
31
A8
30
A7
29
A6
28
A5
27
A4
26
Vss
Note: The # symbol indicates signal is active LOW.
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
1 Meg x 16
512K x 16 x 2 banks
2K or 4K
2K (A0-A10)
2 (BA)
256 (A0-A7)
16MB (X16) SDRAM PART NUMBER
PART NUMBER
MT48LC1M16A1TG S
ARCHITECTURE
1 Meg x 16
GENERAL DESCRIPTION
The 16Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 16,777,216 bits. It
is internally configured as a dual 512K x 16 DRAM with
a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the
512K x 16-bit banks is organized as 2,048 rows by 256
columns by 16 bits. Read and write accesses to the
SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of
16Mb: x16 SDRAM
16MSDRAMx16.p65 – Rev. 8/99
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.