MT9D011 Datasheet, PDF (36/61 Pages) Micron Technology – 1/3-INCH 2-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR

PRELIMINARY
MT9D011
2-MEGAPIXEL DIGITAL IMAGE SENSOR
Feature Description
PLL Generated Master Clock
The MT9D011 has an on-chip PLL that can generate
a master clock in the range of 36 MHz to 40 MHz from
an input reference clock of 4 MHz to 40 MHz. It is pos-
sible to bypass the PLL and use CLKIN as master clock.
This is controlled by Reg0x65[15]. When the PLL is
bypassed (Reg0x65[15] = 1), it is recommended to set
the PLL in power down mode by setting Reg0x65[14] =
1. Default mode is PLL bypassed and in powerdown
mode.
Reg0x66 and Reg0x67 controls the frequency setting
of the generated clock.
PLL Settings
The PLL is controlled through its M, N and P param-
eters, as set in registers 0x66 and 0x67. The PLL output
frequency (fout) has the following relationship to the
input frequency (fin):
fout = fin*M/(2*(N+1)*(P+1))
Not all possible settings are allowed. M must be 16
or higher. Also, the following restrictions on frequen-
cies must be obeyed:
FREQUENCY EQUATION MIN [MHZ]
fPFD
fVCO
fout
fin/(N+1)
2
fPFD*M
110
fVCO/(2*(P+1)
36
MAX [MHZ]
16
220
40
PLL Power-up
The PLL takes time to power up. During this time,
the behavior of its output clock is not guaranteed. The
PLL is in power-down by default and must be turned
on manually. When using the PLL, the correct power-
up sequence after chip reset is as follows:
1. Program PLL frequency settings (Reg0x66 and
Reg0x67)
2. Power up PLL (Reg0x65[14] = 0)
3. Wait for PLL settling time > 150µs
4. Turn off PLL bypass (Reg0x65[15] = 0)
Window Control
Window Start
The row and column start address of the displayed
image can be set by Reg0x01 (Row Start) and Reg0x02
(Column Start).
Window Size
The size of the displayed image can be set by Row
Width Reg0x03 and Column Width Reg0x04. The
default image size is 1600 columns and 1200 rows
(UXGA).
The window start and size registers can be used to
configure an image size between 17 and 1632 columns
and between 2 and 1216 rows.
Pixel Border
When Reg0x20[9:8] are both set, a four pixel border
is added around the specified image. This border can
be used as extra pixels for image processing algo-
rithms. The border is independent of the readout
mode, which means that even in skip, zoom, and bin-
ning modes, a four pixel border is output in the image.
When enabled, the row and column widths are eight
pixels larger than the values programmed in Reg0x03
and Reg0x04. If the border is enabled but not shown in
the image (Rex0x20[9:8] = 01), the horizontal blanking
and vertical blanking values are eight pixels larger than
the values programmed in the blanking registers.
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MT9D011__MI2010_E_2.fm - Rev. A 11/04 EN
36
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