PC28F128J3F75A Datasheet, PDF (31/66 Pages) Micron Technology – Numonyx® Embedded Flash Memory (J3 65nm) Single Bit per Cell (SBC)

Numonyx^® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
8.1
8.1.1
8.1.1.1
Note:
Bus Reads
Reading from flash memory outputs stored information to the processor or chipset, and
does not change any contents. Reading can be performed an unlimited number of
times. Besides array data, other types of data such as device information and device
status are available from the flash.
To perform a bus read operation, CEx (refer to Table 17 on page 30) and OE# must be
asserted. CEx is the device-select control; when active, it enables the flash memory
device. OE# is the data-output control; when active, the addressed flash memory data
is driven onto the I/O bus. For all read states, WE# and RP# must be de-asserted. See
Section 9.2, “Read Operations” on page 35.
Asynchronous Page Mode Read
Unlike J3 130nm devices, J3 65 nm SBC device provides Eight-Word Asynchronous
Page mode only. Array data can be sensed up to eight words (16 Bytes) at a time. This
is the default mode on power-up or reset.
On J3 130nm devices, the Set Enhanced Configuration Register command is used to
enable Eight-Word Page mode upon power-up or reset, however this has no effect on J3
65 nm SBC device anymore.
After the initial access delay, the first word out of the page buffer corresponds to the
initial address. Address bits A[3:1] determine which word is output from the page
buffer for a x16 bus width, and A[3:0] determine which byte is output from the page
buffer for a x8 bus width. Subsequent reads from the device come from the page
buffer. These reads are output on DQ[15:0] for a x16 bus width and DQ[7:0] for a x8
bus width after a minimum delay by changing A[3:1] or A[3:0].
Data can be read from the page buffer multiple times, and in any order.If address bits
A[MAX:4] change at any time, or if CEx# is toggled, the device will sense and load new
data into the page buffer. Asynchronous Page mode is the default read mode on power-
up or reset.
To perform a Page mode read after any other operation, the Read Array command must
be issued to read from the flash array. Asynchronous Page mode reads are permitted in
all blocks and are used to access register information. During register access, only one
word is loaded into the page buffer.
Enhanced Configuration Register
The Enhanced Configuration Register (ECR) is a volatile storage register that when
addressed by the Set ECR command can select between Four-Word Page mode and
Eight-Word Page mode on J3 130nm devices, however this has no effect on J3 65 nm
SBC device.
The ECR is volatile; all bits will be reset to default values when RP# is deasserted or
power is removed from the device. To modify ECR settings, use the Set ECR command.
The Set ECR command is written along with the configuration register value, which is
placed on the lower 16 bits of the address bus A[16:1]. This is followed by a second
write that confirms the operation and again presents the ECR data on the address bus.
After executing this command, the device returns to Read Array mode.
The ECR is shown in Table 18. 8-word page mode Command Bus-Cycle is captured in
Table 19 for backward compatibility reasons.
If the 8-word Asynchronous Page mode is used on J3 65 nm SBC, a Clear Status
Register command must be executed after issuing the Set ECR command.
Jan 2011
208032-03
Datasheet
31