PC28F128J3F75A Datasheet, PDF (25/66 Pages) Micron Technology – Numonyx® Embedded Flash Memory (J3 65nm) Single Bit per Cell (SBC)

Numonyx^® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Figure 8: Single-Word Asynchronous Read Waveform
Address [A]
CEx [E]
OE # [G]
WE# [W]
DQ[15:0] [Q]
BYTE# [F]
RP# [P ]
R1
R2
R3
R4
R7
R6
R11
R5
R12
R 13
R8
R9
R10
Notes:
1.
CE_X low is defined as the
combination of pins CE0,
combination of pins CE0, CE1,
CE1, and CE2 that disable the
daenvdicCeE(2setheaT^ta^ebⁿl^ae^ble17^th,^e“^dC^eh^vii^cp^e.E^Cn^Ea^X b^hil^ge^hT^isru^dt^eh^finT^ea^db^al^se^thf^eor
32-
, 64-, 128-Mb” on page 30).
2.
When reading the flash array a faster t_GLQV (R16) applies. For non-array reads, R4 applies (i.e., Status Register reads,
query reads, or device identifier reads).
Figure 9: 8-Word Asynchronous Page Mode Read
A[MAX :4] [A]
A [3:1] [A]
CEx [E]
OE # [G]
WE# [W]
DQ[15:0] [Q]
RP# [P]
R1
R2
000
R3
R4
R6
R5
R7
1
001
R10
R15
2
110
111
R10
7
8
R8
R9
BYTE # [F]
Notes:
1.
CE_X low is defined as the
combination of pins CE0,
combination of pins CE0, CE1,
CE1, and CE2 that disable the
daenvdicCeE(2setheaT^ta^ebⁿl^ae^ble17^th,^e“^dC^eh^vii^cp^e.E^Cn^Ea^X b^hil^ge^hT^isru^dt^eh^finT^ea^db^al^se^thf^eor
32-
, 64-, 128-Mb” on page 30).
2.
In this diagram, BYTE# is asserted high.
Jan 2011
208032-03
Datasheet
25