MT8VDDT3264AG Datasheet, PDF (28/30 Pages) Micron Technology – DDR SDRAM UNBUFFERED DIMM

128MB, 256MB, 512MB (x64, SR)
184-PIN DDR SDRAM UDIMM
Table 21: Serial Presence-Detect Matrix
“1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”;notes appear on page 28
BYTE
DESCRIPTION
ENTRY(VERSION) MT8VDDT1664A MT8VDDT3264A MT8VDDT6464A
31
32
33
34
35
36-40
41
42
43
44
45
46
47
48–61
62
63
64
65-71
72
73-90
91
92
93
94
95-98
99-127
Module Rank Density
128MB, 256MB,
512MB
Address And Command Setup Time, ^tIS
0.8ns (-335)
(See note 3)
1.0ns (-262/-26A/-265)
Address And Command Hold Time, ^tIH
0.8ns (-335)
(See note 3)
1.0ns (-262/-26A/-265)
Data/data Mask Input Setup Time, ^tDS
0.45ns (-335)
0.5ns (-262/-26A/-265)
Data/Data Mask Input Hold Time, ^tDH
0.45ns (-335)
0.5ns (-262/-26A/-265)
Reserved
Minimum Active/ Auto Refresh Time,
t_RC
60ns (-335/-262)
65ns (-26A/-265)
Minimum Auto Refresh To Active/ Auto
72ns (-335)
Refresh Command Period, ^tRFC
75ns (-262/-26A/-265)
Maximum Cycle Time, ^tCK (MAX)
12ns (-335)
13ns (-262/-26A/-265)
Maximum DQS-DQ Skew Time, ^tDQSQ
0.45ns (-335)
0.5ns (-262/-26A/-265)
Maximum Read Data Hold Skew Factor,
0.55ns (-335)
t_QHS
0.75ns (-262/-26A/-265)
Reserved
DIMM Height
Standard/Low-Profile
Reserved
SPD Revision
Release 1.0
Checksum For Bytes 0-62
-335
-262
-26A
-265
Manufacturer’s JEDEC ID Code
MICRON
Manufacturer’s JEDEC ID Code (cont’d)
(continued)
Manufacturing Location
1 - 12
Module Part Number (ASCII)
PCB Identification Code
Identification Code (continued)
0
Year of Manufacture In BCD
Week of Manufacture In BCD
Module Serial Number
Manufacturer-Specific Data (RSVD)
20
80
A0
80
A0
45
50
45
50
00
3C
41
48
4B
30
34
2D
32
55
75
00
01/11
00
10
04/14
97/A7
C4/D4
F4/04
2C
FF
01 - 0C
Variable Data
Variable Data
00
Variable Data
Variable Data
Variable Data
–
40
80
A0
80
A0
45
50
45
50
00
3C
41
48
4B
30
34
2D
32
55
75
00
01/11
00
10
27/37
BA/CA
E7/F7
17/27
2C
FF
01 - 0C
Variable Data
Variable Data
00
Variable Data
Variable Data
Variable Data
–
80
80
A0
80
A0
45
50
45
50
00
3C
41
48
4B
30
34
2D
32
55
75
00
01/11
00
10
68/78
FB/0B
28/38
58/68
2C
FF
01 - 0C
Variable Data
Variable Data
00
Variable Data
Variable Data
Variable Data
–
NOTE:
1. Value for -26A ^tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns.
2. The value of ^tRAS for -26A and -265 modules is calculated from ^tRC - ^tRP. Actual device spec. value is 40ns.
3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value
is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster
minimum slew rate is met.
4. The value of ^tRP, ^tRCD and ^tRAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR
SDRAM device specification is 15ns.
pdf: 09005aef80867ab3, source: 09005aef80867a99
DD8C16_32_64x64AG.fm - Rev. G 9/04 EN
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.