MT8VDDT3264AG Datasheet, PDF (15/30 Pages) Micron Technology – DDR SDRAM UNBUFFERED DIMM

128MB, 256MB, 512MB (x64, SR)
184-PIN DDR SDRAM UDIMM
Table 13: IDD Specifications and Conditions – 256MB
DDR SDRAM components only
Notes: 1–5, 8, 10, 12, 48; notes appear on pages 19–22; 0°C ≤ T_A ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge; ^tRC = ^tRC
(MIN); ^tCK = ^tCK (MIN); DQ, DM, and DQS inputs changing once per
clock cycle; Address and control inputs changing once every two clock
cycles
OPERATING CURRENT: One device bank; Active-Read-Pre-charge;
Burst = 4; ^tRC = ^tRC (MIN); ^tCK = ^tCK (MIN); IOUT = 0mA; Address and
control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode; ^tCK = ^tCK (MIN); CKE = LOW
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t_{CK =} t_{CK (MIN); CKE = HIGH; Address and other control inputs}
changing once per clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;
Power-down mode; ^tCK = ^tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank;
Active-Precharge; ^tRC = ^tRAS (MAX); ^tCK = ^tCK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing once per clock
cycle; ^tCK = ^tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing once per clock
cycle; ^tCK = ^tCK (MIN); DQ, DM, and DQS inputs changing twice per
clock cycle
AUTO REFRESH CURRENT
t_{REFC =} t_{RFC (MIN)}
t_{REFC = 7.8125µs}
SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four device bank interleaving READs
(BL= 4) with auto precharge,^tRC = minimum ^tRC allowed; ^tCK = ^tCK
(MIN); Address and control inputs change only during Active, READ,
or WRITE commands
SYM
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD5A
IDD6
IDD7
-335
1,000
1,360
32
400
240
480
1,400
1,400
2,040
48
32
3,280
MAX
-262
1,000
1,280
32
360
200
400
1,200
1,200
1,880
48
32
2,800
-26A/
-265 UNITS NOTES
960 mA 20, 42
1,160 mA 20, 42
32
mA 21, 28,
44
360 mA
45
200 mA 21, 28,
44
400 mA 20, 41
1,200 mA 20, 42
1,200 mA
20
1,880 mA
48
mA
32
mA
2,800 mA
20, 44
24, 44
9
20, 43
pdf: 09005aef80867ab3, source: 09005aef80867a99
DD8C16_32_64x64AG.fm - Rev. G 9/04 EN
15
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©2004 Micron Technology. Inc.