MT8VDDT3264AG Datasheet, PDF (24/30 Pages) Micron Technology – DDR SDRAM UNBUFFERED DIMM

SPD Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 12, Data Validity, and Figure 13, Defi-
nition of Start and Stop).
SPD Start Condition
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
SPD Stop Condition
All communications are terminated by a stop condi-
tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
Figure 12: Data Validity
128MB, 256MB, 512MB (x64, SR)
184-PIN DDR SDRAM UDIMM
SPD Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Fig-
ure 14, Acknowledge Response From Receiver).
The SPD device will always respond with an
acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.
Figure 13: Definition of Start and Stop
SCL
SCL
SDA
DATA STABLE
DATA
DATA STABLE
CHANGE
SDA
START
BIT
STOP
BIT
Figure 14: Acknowledge Response From Receiver
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
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DD8C16_32_64x64AG.fm - Rev. G 9/04 EN
24
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