N25Q032A11ESE40G Datasheet, PDF (26/82 Pages) Micron Technology – 32Mb, 1.8V, Multiple I/O Serial Flash Memory

32Mb, 1.8V, Multiple I/O Serial Flash Memory
Nonvolatile and Volatile Registers
Table 15: Flag Status Register Bit Definitions (Continued)
Note 1 applies to entire table
Bit Name
Settings
1 Protection
0 = Clear
1 = Failure or protection error
0 Reserved
Reserved
Description
Error bit: Indicates whether an ERASE or a PROGRAM
operation has attempted to modify the protected array
sector, or whether a PROGRAM operation has attemp-
ted to access the locked OTP space.
Reserved
Notes
4, 5
Notes:
1. Register bits are read by READ FLAG STATUS REGISTER command. All bits are volatile.
2. These program/erase controller settings apply only to PROGRAM or ERASE command cy-
cles in progress, or to the specific WRITE command cycles in progress as shown here.
3. Status bits are reset automatically.
4. Error bits must be reset by CLEAR FLAG STATUS REGISTER command.
5. Typical errors include operation failures and protection errors caused by issuing a com-
mand before the error bit has been reset to 0.
PDF: 09005aef84566617
n25q_32mb_1_8v_65nm.pdf - Rev. E 6/12 EN
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