M25P16-VMN6PBA Datasheet, PDF(22/53 Page) Micron Technology – Micron M25P16 Serial Flash Embedded Memory

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M25P16-VMN6PBA Datasheet, PDF (22/53 Pages) Micron Technology – Micron M25P16 Serial Flash Embedded Memory

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Micron M25P16 Serial Flash Embedded Memory

READ STATUS REGISTER

WIP Bit

The write in progress (WIP) bit indicates whether the memory is busy with a WRITE

STATUS REGISTER cycle, a PROGRAM cycle, or an ERASE cycle. When the WIP bit is set

to 1, a cycle is in progress; when the WIP bit is set to 0, a cycle is not in progress.

WEL Bit

The write enable latch (WEL) bit indicates the status of the internal write enable latch.

When the WEL bit is set to 1, the internal write enable latch is set; when the WEL bit is

set to 0, the internal write enable latch is reset and no WRITE STATUS REGISTER, PRO-

GRAM, or ERASE command is accepted.

Block Protect Bits

The block protect bits are non-volatile. They define the size of the area to be software

protected against PROGRAM and ERASE commands. The block protect bits are written

with the WRITE STATUS REGISTER command.

When one or more of the block protect bits is set to 1, the relevant memory area, as de-

fined in the Protected Area Sizes table, becomes protected against PAGE PROGRAM and

SECTOR ERASE commands. The block protect bits can be written provided that the

HARDWARE PROTECTED mode has not been set. The BULK ERASE command is execu-

ted only if all block protect bits are 0.

SRWD Bit

The status register write disable (SRWD) bit is operated in conjunction with the write

protect (W#) signal. When the SRWD bit is set to 1 and W# is driven LOW, the device is

put in the hardware protected mode. In the hardware protected mode, the non-volatile

bits of the status register (SRWD, and the block protect bits) become read-only bits and

the WRITE STATUS REGISTER command is no longer accepted for execution.

SRWD Bit

The status register write disable (SRWD) bit is operated in conjunction with the write

protect (W#/VPP) signal. When the SRWD bit is set to 1 and W#/V PP is driven LOW, the

device is put in the hardware protected mode. In the hardware protected mode, the

non-volatile bits of the status register (SRWD, and the block protect bits) become read-

only bits and the WRITE STATUS REGISTER command is no longer accepted for execu-

tion.

PDF: 09005aef8456656c

m25p16.pdf - Rev. H 1/14 EN

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