MT48LC64M4A2 Datasheet, PDF (21/62 Pages) Micron Technology – SYNCHRONOUS DRAM

256Mb: x4, x8, x16
SDRAM
T0
T1
T2
T3
CLK
T4
T5
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
CAS Latency = 2
DOUT
n
DOUT
a
DOUT
x
DOUT
m
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
DOUT
n
DOUT
a
CAS Latency = 3
NOTE: Each READ command may be to any bank. DQM is LOW.
Figure 8
Random READ Accesses
DOUT
x
DOUT
m
DON’T CARE
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
21
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©2002, Micron Technology, Inc.