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MT48LC64M4A2 Datasheet, PDF (1/62 Pages) Micron Technology – SYNCHRONOUS DRAM | |||
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256Mb: x4, x8, x16
SDRAM
SYNCHRONOUS
DRAM
FEATURES
⢠PC66-, PC100-, and PC133-compliant
⢠Fully synchronous; all signals registered on
positive edge of system clock
⢠Internal pipelined operation; column address can
be changed every clock cycle
⢠Internal banks for hiding row access/precharge
⢠Programmable burst lengths: 1, 2, 4, 8, or full page
⢠Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
⢠Self Refresh Mode
⢠64ms, 8,192-cycle refresh
⢠LVTTL-compatible inputs and outputs
⢠Single +3.3V ±0.3V power supply
OPTIONS
MARKING
⢠Configurations
64 Meg x 4 (16 Meg x 4 x 4 banks) 64M4
32 Meg x 8 ( 8 Meg x 8 x 4 banks) 32M8
16 Meg x 16 ( 4 Meg x 16 x 4 banks) 16M16
⢠WRITE Recovery (tWR)
tWR = â2 CLKâ1
A2
⢠Package/Pinout
54-pin TSOP II OCPL2 (400 mil)
60-ball FBGA (8mm x 16mm) (x4, x8)
54-ball FBGA (8mm x 14mm) (x16 only)
TG
FB4, 5
FG3
⢠Timing (Cycle Time)
7.5ns @ CL = 2 (PC133)
-7E
7.5ns @ CL = 3 (PC133)
-75
⢠Self Refresh
Standard
Low power
None
L3
⢠Operating Temperature
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
None
IT3
NOTE: 1. Refer to Micron Technical Note TN-48-05.
2. Off-center parting line.
3. Consult Micron for availability.
4. Not available in x16 configuration.
5. Actual FBGA part marking shown on page 58.
Part Number Example:
MT48LC16M16A2TG-75
MT48LC64M4A2 â 16 Meg x 4 x 4 banks
MT48LC32M8A2 â 8 Meg x 8 x 4 banks
MT48LC16M16A2 â 4 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web site:
www.micron.com/dramds
PIN ASSIGNMENT (Top View)
54-Pin TSOP
x4 x8 x16
- - VDD
1
NC DQ0 DQ0
2
- - VDDQ
3
NC NC DQ1
4
DQ0 DQ1 DQ2
5
- - VssQ
6
NC NC DQ3
7
NC DQ2 DQ4
8
- - VDDQ
9
NC NC DQ5
10
DQ1 DQ3 DQ6
11
- - VssQ
12
NC NC DQ7
13
- - VDD
14
NC NC DQML
15
- - WE#
16
- - CAS#
17
- - RAS#
18
- - CS#
19
- - BA0
20
- - BA1
21
- - A10
22
--
A0
23
--
A1
24
--
A2
25
--
A3
26
- - VDD
27
x16 x8 x4
54
Vss - -
53
DQ15 DQ7 NC
52
VssQ - -
51
DQ14 NC NC
50
DQ13 DQ6 DQ3
49
VDDQ - -
48
DQ12 NC NC
47
DQ11 DQ5 NC
46
VssQ - -
45
DQ10 NC NC
44
DQ9 DQ4 DQ2
43
VDDQ - -
42
DQ8 NC NC
41
Vss - -
40
NC - -
39
DQMH DQM DQM
38
CLK - -
37
CKE - -
36
A12 - -
35
A11 - -
34
A9 - -
33
A8 - -
32
A7 - -
31
A6 - -
30
A5 - -
29
A4 - -
28
Vss - -
Note: The # symbol indicates signal is active LOW. A dash (â)
indicates x8 and x4 pin function is same as x16 pin function.
64 Meg x 4
32 Meg x 8
16 Meg x 16
Configuration
16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
Refresh Count
8K
8K
8K
Row Addressing
8K (A0âA12)
8K (A0âA12)
8K (A0âA12)
Bank Addressing
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
ColumnAddressing 2K (A0âA9, A11)
1K (A0âA9)
512 (A0âA8)
KEY TIMING PARAMETERS
SPEED
GRADE
-7E
-75
-7E
-75
CLOCK
FREQUENCY
143 MHz
133 MHz
133 MHz
100 MHz
ACCESS TIME
CL = 2* CL = 3*
â
â
5.4ns
6ns
5.4ns
5.4ns
â
â
SETUP
TIME
1.5ns
1.5ns
1.5ns
1.5ns
HOLD
TIME
0.8ns
0.8ns
0.8ns
0.8ns
*CL = CAS (READ) latency
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 â Rev. E; Pub. 3/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
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