MT48H4M16LFB4-8ITH Datasheet, PDF (14/62 Pages) Micron Technology – Mobile SDRAM MT48H4M16LF – 1 Meg x 16 x 4 banks

64Mb: 4 Meg x 16 Mobile SDRAM
Commands
Commands
Table 5 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional truth tables appear following “Opera-
tions” on page 18; these tables provide current state/next state information.
Table 5:
Truth Table 1 – Commands and DQM Operation
Note 1; notes appear below table
Name (Function)
CS#
COMMAND INHIBIT (NOP)
H
NO OPERATION (NOP)
L
ACTIVE (Select bank and activate row)
L
READ (Select bank and column, and start READ burst) L
WRITE (Select bank and column, and start WRITE burst) L
BURST TERMINATE or deep power-down
L
(Enter deep power-down mode)
PRECHARGE (Deactivate row in bank or banks)
L
AUTO REFRESH or SELF REFRESH
L
(Enter self refresh mode)
LOAD MODE REGISTER/LOAD EXTENDED MODE
L
REGISTER
Write enable/output enable
X
Write inhibit/output High-Z
X
RAS# CAS# WE#
X
X
X
H
H
H
L
H
H
H
L
H
H
L
L
H
H
L
L
H
L
L
L
H
L
L
L
X
X
X
X
X
X
DQM
X
X
X
L/H
L/H
X
X
X
X
L
H
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
DQ
X
X
X
X
Valid
X
Notes
3
4
4
9, 10
Bank, A10 X
5
X
X
6, 7
Op-code X
2
X
Active 8
X
High-Z 8
Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH and deep power-down.
2. A0–A11 define op-code written to mode register.
3. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0–A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersis-
tent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank
is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
8. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock
delay). LDQM controls DQ0–7, UDQM controls DQ8–15.
9. This command is BURST TERMINATE when CKE is HIGH and deep power-down when CKE is
LOW.
10. The purpose of the BURST TERMINATE command is to stop a data burst; thus, the command
could coincide with data on the bus. However, the DQ column reads a “Don’t Care” state to
illustrate that the BURST TERMINATE command can occur when there is no data present.
PDF: 09005aef8237ed98/Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. C 10/07 EN
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