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MT28F160C34 Datasheet, PDF (1/28 Pages) Micron Technology – FLASH MEMORY
ADVANCE‡
1 MEG x 16
3V ENHANCED+ BOOT BLOCK FLASH MEMORY
FLASH MEMORY
MT28F160C34
FEATURES
• Thirty-nine erase blocks:
Eight 4K-word parameter blocks
Thirty-one 32K-word main memory blocks
• VCC, VCCQ and VPP voltages:
3.3V ±5% VCC
3.3V ±5% VCCQ
1.65V–3.465V and 12V VPP
• Address access times:
90ns at 3.3V ±5%
• Low power consumption:
Standby and deep power-down mode < 1µA
(typical ICC)
Automatic power saving feature (APS mode)
• Enhanced WRITE/ERASE SUSPEND (1µs typical)
• 128-bit OTP area for security purposes
• Industry-standard command set compatibility
• Software/hardware block protection
OPTIONS
• Timing
90ns access
• Boot Block Starting Address
Top (FFFFFh)
Bottom (00000h)
• Package
46-ball FBGA (6 x 8 ball grid)
• Temperature Range
Extended (-40ºC to +85ºC)
NUMBER
-9
T
B
FD
ET
Part Number Example:
MT28F160C34FD-9 TET
GENERAL DESCRIPTION
The MT28F160C34 is a nonvolatile, electrically block-
erasable (flash), programmable memory containing
16,777,216 bits organized as 1,048,576 words (16 bits).
The MT28F160C34 is manufactured on 0.22µm process
technology in a 46-ball FBGA package.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM), which simplifies these operations and
relieves the system processor of secondary tasks. The
BALL ASSIGNMENT (Top View)
46-Ball FBGA
1
2
3
4
5
6
7
8
A
A13 A11
A8
VPP
WP# A19
A7
A4
B
A14 A10 WE# RP# A18 A17
A5
A2
C
A15 A12
A9
A6
A3
A1
D
A16 DQ14 DQ5 DQ11 DQ2 DQ8 CE#
A0
E
VCCQ DQ15 DQ6 DQ12 DQ3 DQ9 DQ0
VSS
F
VSS
DQ7 DQ13 DQ4
VCC DQ10 DQ1 OE#
(Ball Down)
NOTE: See page 3 for Ball Description Table.
See last page for mechanical drawing.
WSM status can be monitored by an on-chip status reg-
ister to determine the progress of program/erase tasks.
The device is equipped with 128 bits of one time
programmable (OTP) area. The soft protection feature
for blocks will mark them as read-only by configuring soft
protection registers with command sequences.
ARCHITECTURE
The MT28F160C34 flash contains eight 4K-word
parameter blocks and thirty-one 32K-word blocks.
Memory is organized by using a blocked architecture to
allow independent erasure of selected memory blocks.
Any address within a block address range selects that
block for the required READ, WRITE, or ERASE operation
(see Figure 1).
1 Meg x 16 3V Enhanced+ Boot Block Flash Memory
MT28F160C34_3.p65 – Rev. 3, Pub. 8/01
1
©2001, Micron Technology, Inc.
‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE
BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.