RV-4162 Datasheet, PDF (8/39 Pages) MICORO CRYSTAL SWITZERLAND – Ultra Small Real Time Clock

Micro Crystal
Ultra Small Real Time Clock / Calendar Module
RV-4162
3. REGISTER ORGANIZATION
The RV-4162 user interface consists of 16 memory mapped registers which include clock, calibration, alarm,
watchdog, flags, and square wave control.
First 8 registers are the Clock Section at address 00h through 07h. These registers are accessed indirectly via a
set of transfer registers.
Clock Section (addresses 00h through 07h):
These registers are coded in BCD format and contain the century, year, month, day / date, hours, minutes,
seconds and tenths / hundredths of seconds in 24-hour format. Corrections for 28, 29 (leap year), 30 or 31 day of
months are made automatically. These registers are accessed indirectly through transfer registers.
Next 8 registers are the control section at address 08h through 0Fh.
Control Section (addresses 08h through 0Fh):
These registers are coded in binary format and provide status, frequency compensation, alarm and control of the
peripheral functions including the programmable clock output and watchdog functions.
The CMOS IC contains 16 8-bit RAM registers. These registers are carried out double: internal counters and
external user accessible registers.
All sixteen registers are designed as addressable 8-bit parallel registers, although, not all bits are implemented.
The address counter is automatically incremented after each written or read data byte.
The internal registers keeping track of the time based on the 32.768 kHz clock oscillator and the divider chain. The
external registers are independent of the internal counters except that they are updated periodically by the
simultaneous transfer of the incremented internal data. To prevent data transition during Interface access, the
content of the external register is kept stable whenever the address being read is a clock address (00h to 07h).
The update of the external register will resume either when the address-pointer increments to a non-clock address
or Interface communication is terminated by sending a “STOP condition”.
After “WRITE” to the external register, when the “STOP condition” terminates the Interface communication, the
content of the modified external registers is copied into the corresponding internal registers. The divider chain of
the 32.768 kHz oscillator will be reset upon the completion of a “WRITE” to any clock address (00h to 07h).
3.1. REGISTER ACCESS
During normal operation when the user is not accessing the device, the transfer registers are kept updated with a
copy of the Clock Counter data.
At the start of an I²C read or write cycle, the updating is halted and the present time & date is frozen in the transfer
registers. Halting the updates at the start of an I²C access is to ensure that all the time & date data transferred out
during a read sequence comes from the same instant in time.
When writing to the device, each bit is shifted into the RV-4162's I²C Interface on the rising edge of the SCL signal.
On the 8th clock cycle, each byte is transferred from the I²C block into the register addressed by the address
pointer.
Data written to the Clock Registers (addresses 00h - 07h) is held in the transfer registers until the address pointer
increments to 08h, or when STOP condition from I²C Interface is received. At which time the data in the transfer
registers are simultaneously copied into the Clock Counters and then the clock is restarted.
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