PL613-01 Datasheet, PDF (9/20 Pages) Microchip Technology – 1.8V to 3.3V, PicoPLL, 3-PLL, 200 MHz, 8 Output Clock IC

4.0 LAYOUT RECOMMENDATIONS
The following guidelines are designed to help create a
performance-optimized PCB design.
4.1 Signal Integrity and Termination
Considerations
• Keep traces short.
• Trace = Inductor. With capacitive loads, this
creates ringing.
• Long trace = long transmission line. Without
proper termination, this causes reflections that
look like ringing.
• Design long traces (greater than one inch) as
striplines or microstrips with defined impedance.
• Match trace at one side to avoid reflections
bouncing back and forth.
4.2 Decoupling and Power Supply
Considerations
• Place decoupling capacitors as close as possible
to the V_DD pin(s) to limit noise from the power
supply.
• Multiple V_DD pins should be decoupled separately
for best performance.
• The addition of resistors in series with V_DD can
help prevent noise from other board sources.
- Traditionally, ferrite beads are used for this
purpose, but with the PL613-01 the results
are better when using resistors.
Typical CMOS Termination
Place Series Resistor as close as possible to CMOS output.
CMOS Output Buffer
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To CMOS Input
Series Resistor
Use value to match output buffer impedance
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FIGURE 4-1:
Typical CMOS Termination.
Crystal Tuning Circuit
Series and parallel capacitors used to fine tune the crystal load to the circuit load.
Crystal
CST
CPT
XIN
1
XOUT
8
CPT
CST: Series Capacitor that is used to lower circuit load to match crystal load. Raises
frequency offset. This can be eliminated by using a crystal with a C_LOAD of equal or
greater value than the oscillator.
CPT: Parallel Capacitors that are used to raise the circuit load to match the crystal load.
Lowers frequency offset.
FIGURE 4-2:
Crystal Tuning Circuit.
 2016 Microchip Technology Inc.
PL613-01
4.3 Layout Example
CLK5
CLK6
CLK4
CLK3
CLK2
FIGURE 4-3:
PL613-01 Layout Example.
U1 = PL613-01 in QFN-16L. In this example, all eight
outputs are used.
C1a, C2a, C3a = 0.1 μF and C1b, C2b, C3b = 1 μF for
power supply decoupling. The vias connected to the
capacitors go to the ground plane inside the PCB.
Rp1, Rp2, Rp3 = 10Ω for power supply filtering. The
power supply filter is a first order low pass filter with
–3 dB at 30 kHz. It is important that the frequencies of
the loop bandwidth of the PLLs are filtered properly.
The loop bandwidth of the PLLs is in the range of
100 kHz to 1 MHz depending upon the programmed
configuration. The vias connected to Rp1, Rp2, and
Rp3 go to the V_DD plane inside the PCB.
R0 ~ R7 = 30Ω for matching CLK0 ~ CLK7 outputs to
the PCB trace impedance. Place the resistors as close
as possible to the IC pins and design the traces to the
DS20005650A-page 9